The number of triggers is configurable since https://github.com/riscv-software-src/riscv-isa-sim/pull/1219.
The trigger description was for the limited implementation when developing the extension. All trigger types are supported now. The information isn't very useful anymore.
Signed-off-by: YenHaoChen <39526191+YenHaoChen@users.noreply.github.com>
Before this patch, spike just had an "Xbitmanip" extension which
covered everything in the proposed bitmanip extension that hadn't been
ratified. The problem is that if you want to model (or verify) a
processor that targetted just some of the proposed bitmanip extension,
you couldn't configure Spike to do that.
For example, the lowRISC Ibex processor has several different
configurations. The "balanced" configuration targetted Zba, Zbb, Zbs,
Zbf and Zbt of the 0.92 spec. With the Zba, Zbb and Zbs ratified,
we'll now be able to use an ISA string like
rv32imc_Zba_Zbb_Zbs_XZbf_XZbt
and Spike will correctly fail to decode instructions like 'bcompress',
which would have been decoded with Xbitmanip.
This patch adds a new custom extension name for each part of the
extension that wasn't fully ratified. These have an 'X' prefix so, for
example, the bit permutation instructions that were proposed as Zbp
can be found under XZbp.
Specifying "Xbitmanip" gets all of these extensions, so its behaviour
should be unchanged.
Note that the slo(i) / sro(i) instructions have been moved from the
proposed Zbb to XZbp. This matches a comment in the Change History
section of v0.93 of the bitmanip spec: it seems that the authors
forgot to also move them in Table 2.1 (which gives the lists of
instructions for each extension). This change won't break anything
that currently exists, but it took quite a while to figure out what
was going on so I thought I'd leave a breadcrumb trail for the next
engineer!
The bulk of the patch is just defining some more entries in the
isa_extension_t enum and rewriting each of the instructions to depend
on the relevant entry. This is mostly a straight textual replacement
but it's slightly more complicated for things like the "pack"
instruction that are defined by several different proposed extensions.
Krypto 1.0 changes: Entropy source CSR, name.
List scalar crypto instruction groupings, as there is no single K extension.
Co-authored-by: Markku-Juhani O. Saarinen <mjos@mjos.fi>
* Priv virtual memory updates
* Priv 1.12 requires page faults when the address translation process
reaches a PTE with any reserved bit set
* Svpbmt uses two PTE bits, but otherwise has no effect on Spike (since
Spike is sequentially consistent and does not model PMAs)
* Add Svinval instructions
Even though I updated riscv-opcodes separately, I merged the new
defines into riscv/encoding.h manually, because riscv-opcodes seems
to be a step ahead of riscv-isa-sim for a few vector opcodes, causing
conflicts when regenerating encoding.h...
If that gets fixed, and encoding.h gets regenerated automatically, I can
remove it from this PR to avoid conflicts.
* Svinval: use #include rather than copying code
..for the Svinval functions that are implemented in ways that just
mimic SFENCE/HFENCE instructions
Thanks to @aswaterman for the suggestion
Brief:
- This commit adds spike support for the scalar cryptography extension.
See the riscv-crypto repository (https://github.com/riscv/riscv-crypto)
for more information on this extension.
- It is based on the experimental patch which has so far been kept in the
riscv-crypto repository. Now that scalar crypto is nearly at the "freeze"
stage and entering opcode consistency review, it makes sense to start
upstreaming our experimental version.
- In terms of compiler support - we are using an experimental patch in
the riscv-crypto repository at the moment, others are working on an
upstream appropriate version.
Details:
- Add support for dedicated scalar crypto instructions.
- Add very basic support for the entropy source (entropy_source.h).
Much of the behaviour of this is implementation specific. This model
aims to provide the bare minimum of functionality which can be used to
quickly develop software. It uses /dev/urandom as its entropy source for
now.
- Scalar crypto is unique in that it _borrows_ instructions from the
Bitmanipulation extension. This is currently _not_ encoded in the patch,
as I didn't want to damage anything in Bitmanip which is currently under
review. However, I've added a macro in riscv/decode.h called
"require_either_extension(A,B)", which allows instructions to be valid
opcodes iff they are in one or both extensions.
On branch scalar-crypto
Changes to be committed:
modified: README.md
modified: riscv/decode.h
modified: riscv/encoding.h
new file: riscv/entropy_source.h
new file: riscv/insns/aes64im.h
new file: riscv/insns/aes64ks1i.h
new file: riscv/insns/aes64ks2.h
new file: riscv/insns/aes_common.h
new file: riscv/insns/aesds.h
new file: riscv/insns/aesdsm.h
new file: riscv/insns/aeses.h
new file: riscv/insns/aesesm.h
new file: riscv/insns/sha256sig0.h
new file: riscv/insns/sha256sig1.h
new file: riscv/insns/sha256sum0.h
new file: riscv/insns/sha256sum1.h
new file: riscv/insns/sha512sig0.h
new file: riscv/insns/sha512sig0h.h
new file: riscv/insns/sha512sig0l.h
new file: riscv/insns/sha512sig1.h
new file: riscv/insns/sha512sig1h.h
new file: riscv/insns/sha512sig1l.h
new file: riscv/insns/sha512sum0.h
new file: riscv/insns/sha512sum0r.h
new file: riscv/insns/sha512sum1.h
new file: riscv/insns/sha512sum1r.h
new file: riscv/insns/sm3p0.h
new file: riscv/insns/sm3p1.h
new file: riscv/insns/sm4_common.h
new file: riscv/insns/sm4ed.h
new file: riscv/insns/sm4ks.h
modified: riscv/processor.cc
modified: riscv/processor.h
modified: riscv/riscv.mk.in
Christian Herber
Ved Shanbhogue
Chao Du
akifejaz
Katharina
YenHaoChen
brs
Andrew Waterman
Weiwei Li
Tommy Murphy
YenHaoChen
Tim Newsome
Scott Johnson
soberl
Rupert Swarbrick
Mohit Singla
Markku-Juhani O. Saarinen
Daniel Lustig
ChunPing Chung
Chih-Min Chao
Ben Marshall
Kito Cheng