Andrew Waterman
|
740f981cfd
|
[sim] renamed to riscv-isa-run
|
15 years ago |
|
Andrew Waterman
|
c0ebf99d6b
|
[xcc] minor performance tweaks
|
15 years ago |
|
Andrew Waterman
|
20bc10dc08
|
[xcc] fixed simulator build time
|
15 years ago |
|
Andrew Waterman
|
f23ae8b0bc
|
[xcc] tlb now stores host addresses
|
15 years ago |
|
Andrew Waterman
|
d6fd350f0c
|
[xcc] cleaned up mmu code
|
15 years ago |
|
Andrew Waterman
|
e665e552b3
|
[xcc] fix configure scripts
|
15 years ago |
|
Andrew Waterman
|
a23f18a6a6
|
[xcc] instructions now set PC explicitly
|
15 years ago |
|
Andrew Waterman
|
3fcb2cbe79
|
[sim, opcodes] made sim more decoupled from opcodes
|
15 years ago |
|
Andrew Waterman
|
82403eb338
|
[sim] fix writeback after ipi clearing
|
15 years ago |
Andrew Waterman
|
ca156be905
|
[sim] add ability to clear IPIs
|
15 years ago |
|
Andrew Waterman
|
f1bb8270a1
|
[sim] fault on failed addr translations
previously, a bad PTE would segfault the simulator, rather than sending
the fault to the OS.
|
15 years ago |
|
Andrew Waterman
|
2641a9b24f
|
[sim] minor sim cleanup
|
15 years ago |
|
Andrew Waterman
|
e8d6925f0e
|
[sim,opcodes] improved sim build and run performance
|
15 years ago |
|
Andrew Waterman
|
605d638068
|
[fesvr,xcc,sim] fixed multicore sim for akaros
|
15 years ago |
|
Andrew Waterman
|
c42bce582a
|
[sim,xcc] add rdcycle/rdtime/rdinstret
|
15 years ago |
Andrew Waterman
|
bb09521614
|
[sim] more fp<->int fixes
|
15 years ago |
|
Andrew Waterman
|
996c3808ad
|
[sim] more fp conversion bugs fixed
|
15 years ago |
Yunsup Lee
|
93f1d11a4f
|
[sim] change default hwvl
|
15 years ago |
|
Yunsup Lee
|
f8ca42bf48
|
[sim] vlen calc reflects the hardware
|
15 years ago |
|
Andrew Waterman
|
6928933df6
|
[sim] fixed fcvt rounding bugs
|
15 years ago |
|
Yunsup Lee
|
dd1da16567
|
[opcodes,pk,sim] add more vector traps (for #banks, illegal instructions)
|
15 years ago |
|
Andrew Waterman
|
6e85b4332f
|
[sim,pk] cleanups & initial virtual memory support
|
15 years ago |
|
Yunsup Lee
|
7a589027a7
|
[sim,xcc] change cond. mov inst format, add implementation
|
15 years ago |
|
Yunsup Lee
|
80b00e616e
|
[opcodes,pk,sim,xcc] resolve a conflict
|
15 years ago |
|
Yunsup Lee
|
29d89ec1e6
|
[libs,opcodes,pk,sim,xcc] add mov*,fmov*, shuffle vec insts
|
15 years ago |
|
Andrew Waterman
|
eb601cb532
|
[sim] initial support for virtual memory
|
15 years ago |
|
Andrew Waterman
|
57b8698931
|
[sim] stubs for perfctr instructions
|
15 years ago |
|
Andrew Waterman
|
25123f03b9
|
tweaked encoding of rdcycle & cousins
|
15 years ago |
|
Andrew Waterman
|
ef2e75f0bd
|
[sim] fixed building sim without cache simulators
|
15 years ago |
|
Andrew Waterman
|
46f2fb1d9e
|
[sim] hacked in a dcache simulator
|
15 years ago |
|
Andrew Waterman
|
913ee989dd
|
[xcc,sim,opcodes] added c.addiw
|
15 years ago |
|
Andrew Waterman
|
d5518cd4d9
|
[xcc,sim,opcodes] added more RVC instructions
|
15 years ago |
|
Andrew Waterman
|
c0cd05e70b
|
[sim] fixed divw/remw crashing simulator
|
15 years ago |
|
Andrew Waterman
|
c6b549289a
|
[xcc,sim] rv64 'w' instruction semantics changed
they no longer require their inputs to be canonicalized 32b values, so
this speeds up mixed int/long code sequences.
|
15 years ago |
|
Andrew Waterman
|
0433532951
|
[xcc,sim,opcodes] added rvc conditional branches
|
15 years ago |
|
Andrew Waterman
|
95d58037b2
|
[sim] removed undefined behavior for non-canonical inputs
|
15 years ago |
|
Andrew Waterman
|
6e2844c1b5
|
[sim] added "str" debug command
it prints the c string starting at the specified memory address.
|
15 years ago |
|
Andrew Waterman
|
5c96429584
|
[sim] fixed jalr immediate bug
|
15 years ago |
|
Andrew Waterman
|
481c9e8fd8
|
[sim] added icache simulator (disabled by default)
|
15 years ago |
|
Andrew Waterman
|
402b4e8600
|
[xcc,pk,sim] added privileged cflush instruction
|
15 years ago |
|
Andrew Waterman
|
f5f9ed0a0d
|
[xcc,sim] fixed RM field
|
15 years ago |
|
Andrew Waterman
|
5fe6c52270
|
[xcc,sim] rvc loads and stores
|
15 years ago |
|
Andrew Waterman
|
06062a1b5c
|
[sim,pk] fixed minor pk bugs and trap codes
|
15 years ago |
|
Andrew Waterman
|
2032e6c6b7
|
[sim] fixed FSR exception field bug
|
15 years ago |
|
Andrew Waterman
|
66eda0b75e
|
[xcc,sim,opcodes] more rvc instructions and bug fixes
|
15 years ago |
|
Yunsup Lee
|
4b534147c0
|
[sim] add disable option for vector
|
15 years ago |
|
Yunsup Lee
|
7198e5091f
|
[sim] set SR_EV for uts
|
15 years ago |
|
Yunsup Lee
|
68f504c52e
|
[sim] add vector traps to vector instructions
|
15 years ago |
|
Yunsup Lee
|
e9567ce7bb
|
[sim] add vt stuff
|
15 years ago |
|
Andrew Waterman
|
c8de0ef0fa
|
[xcc, sim] added rvc insn c.li; misc fixes
|
15 years ago |
