Prior this patch it was impossible to enter debug mode when mseccfg.MML
was set. The reason is that debug ROM requires both RW and X permissions
for debug module to function properly (for example for progbuf
execution).
This patch relaxes pmp checks and allows unconditional access to debug
firmware area whenever the processor is in debug state.
Fib about the address of the counter-config CSRs so that permission
checks will succeed in S-mode and so the correct mcounteren bit is
checked for the cycle config CSR.
Fixes#2312
Signed-off-by: Andrew Waterman <andrew@sifive.com>
check_load_reservation's reservable-fault throw was passing the raw
rs1 value to *tval. Compute the transformed vaddr via
generate_access_info and use its transformed_vaddr/effective_virt
for the trap, per zpm.adoc pm_csr_hw_apply.
Based on
https://github.com/aswaterman/riscv-misc/blob/main/isa/zvfbfa.adoc
"When altfmt=1 and SEW=8, all vector floating-point instructions become
reserved, except for the following, which are redefined to use the BF16
format for any operand that would otherwise have used the FP16 format:
vfwcvt.f.x[u].v
vfncvt.x[u].f.w
vfncvt.rtz.x[u].f.w
"
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
The root node advertises #address-cells = <2>, and memory nodes already encode addresses as high/low 32-bit cells. However, linux,initrd-start and linux,initrd-end were emitted as a single cell, which truncates initrd addresses when the memory region is placed above 4 GiB.
Emit these chosen properties using the same high/low cell representation so Linux can boot with initrd images located in high memory.
* Add 'spmp' in isa string parsing for SPMP extension
* Add PMP_Entry CSRs of spmp
* Implement SPMP matching logic
* Update implementation to spec rc5 version
According to the Zvdota/Zvbdota isa spec, RVBNA may raises
invalid/overflow exceptions.
Add the missing set_fp_exceptions after RVBNA in ZVLDOT_LOOP and
ZVBDOT_LOOP to propagate softfloat exception flags to the processor
state. Without this, FP exceptions raised during RVBNA accumulation
are silently dropped.
Signed-off-by: Max Chou <max.chou@sifive.com>
Chih-Min Chao
Andrew Waterman
Binno
mslijepc
Anatoly Parshintsev
Vladimir Efimov
James Robinson
Zhibo Hong
Max Chou