riscv-isa-sim

Commit Graph

Author	SHA1	Message	Date
Sevan Janiyan	36c40295b4	configure.ac: update m4_include paths	1 year ago
Sevan Janiyan	91091dc852	m4/ax_check_compile_flag.m4: Update To latest version from autoconf-archive.	1 year ago
Sevan Janiyan	73de0ffcdb	m4/ax_boost_base.m4: Update To latest version from autoconf-archive.	1 year ago
Sevan Janiyan	efa8eff405	move autoconf-archive extensions to m4/ Follow usual convention, cleans up root directory.	1 year ago
Andrew Waterman	bfb67c1954	Merge pull request #1902 from chihminchao/extend-bf16 Extend bf16	1 year ago
Chih-Min Chao	1b81e407db	softfloat: extend bf16 APIs also add fxx_neg helper functions Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	1 year ago
Chih-Min Chao	d42570325b	softfloat: change files mode from 755 to 644 Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	1 year ago
Andrew Waterman	cd692c41d6	Merge pull request #1828 from Timmmm/instruction_limit Add instruction limit	1 year ago
Tim Hutt	fdbcde27ce	Add instruction limit Adds an optional --instructions=N CLI argument which will stop the simulation after N instructions. This is useful for benchmarking and profiling and sometimes debugging.	2 years ago
Andrew Waterman	18f4d0ff13	Merge pull request #1904 from YenHaoChen/pr-vcompress vcompress.vm: Check vstart value even if vl = 0	1 year ago
YenHaoChen	3c8562456a	vcompress.vm: Check if there is any vector extension before using vector CSRs	1 year ago
Andrew Waterman	d182829e68	Merge pull request #1907 from kassasAndes/fix-bitmanip-zbs [riscv\|insns] Fix zbs immediate instructions: bclri, bexti, binvi, an…	1 year ago
kassas	2687fa3c48	[riscv\|insns] Fix zbs immediate instructions: bclri, bexti, binvi, and besti for shamt condition	1 year ago
Andrew Waterman	da03b420c2	Merge pull request #1905 from riscv-software-src/fix-pm-misaligned Fix pointer masking for misaligned accesses	1 year ago
Andrew Waterman	aa9918bd54	Fix pointer masking for misaligned accesses Pointer masking needs to be reapplied after computing the address of the tail of a misaligned access in case there's a carry-out into the MSBs. Resolves #1895	1 year ago
Andrew Waterman	10109ae670	Merge pull request #1903 from zqb-all/help-msg-for-dm-no-hasel Fix help message for --dm-no-hasel	1 year ago
YenHaoChen	1434a76e78	Revert "vcompress.vm: Check if there is any vector extension before using vector CSRs" This reverts commit `a17842c0c5`.	1 year ago
Mark Zhuang	2b773d9372	Fix help message for --dm-no-hasel	1 year ago
Jerry Zhao	58da6a2232	Merge pull request #1546 from nibrunieAtSi5/patch-2	1 year ago
Nicolas Brunie	fd077496cd	UB in negate in mulh/mulhsu Ensuring No negation on -2^63(int64_t) is performed during mulh/mulhsu Signed-off-by: Nicolas Brunie <82109999+nibrunieAtSi5@users.noreply.github.com> Update riscv/arith.h Signed-off-by: Nicolas Brunie <82109999+nibrunieAtSi5@users.noreply.github.com>	2 years ago
Andrew Waterman	49727e8c61	Merge pull request #1889 from ved-rivos/010925 (Guest)Page fault cause by Svnapot occur before A/D update	1 year ago
Ved Shanbhogue	0bbf0d64b4	(Guest)Page fault cause by Svnapot occur before A/D update	1 year ago
Andrew Waterman	fa05e4e4f9	Merge pull request #1887 from fly-1011/fix-hvip-lcofi Fix LCOFI bit implementation in hvip register	1 year ago
room	34195bb81a	Fix LCOFI bit implementation in hvip register	1 year ago
Jerry Zhao	b81b5a0686	Merge pull request #1864 from riscv-software-src/ext_csr_reset Add extension_t csrs in reset(), not register_extension()	1 year ago
Andrew Waterman	4cf4915212	Merge pull request #1881 from riscv-software-src/spike-dasm-strict Add spike-dasm --strict option	1 year ago
Andrew Waterman	8ad998f0e7	Add --strict command-line arg to spike-dasm	1 year ago
Andrew Waterman	1e589aa502	Support strict disassembly in disassembler_t	1 year ago
Andrew Waterman	dc094609b0	Merge pull request #1880 from riscv-software-src/fix-xdebugver Set dcsr.xdebugver to 4, as it ought to be	1 year ago
Andrew Waterman	0fea35ddfb	Set dcsr.xdebugver to 4, as it ought to be See discusson on #1878. This restores the behavior prior to `ec292be4fd`, which inadvertently changed the value to 1. Resolves #1878	1 year ago
Jerry Zhao	a2dcf1fd70	Merge pull request #1871 from XYenChi/patch-1	1 year ago
XYenChi	422c71162f	Fix comment op name Fix op name in the comment Signed-off-by: XYenChi <oriachiuan@gmail.com>	1 year ago
Andrew Waterman	fe49242954	Merge pull request #1870 from riscv-software-src/ci-macos-13 Bump CI version to MacOS 13	1 year ago
Andrew Waterman	df2b69b038	Merge pull request #1866 from chihminchao/prioritize-misaligned-superpage mmu: raise the prioity of misaligned superpage	1 year ago
Andrew Waterman	b2b612631b	Bump CI version to MacOS 13 See https://github.com/actions/runner-images/issues/10721	1 year ago
Chih-Min Chao	6fd2bc9882	mmu: raise the prioity of misaligned superpage Based on the change in ttps://github.com/riscv/riscv-isa-manual/pull/1742 The priority of misaligned superpage is higer that Zicfiss cases Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	1 year ago
Jerry Zhao	a10dfd04e7	Add extension_t csrs in reset(), not register_extension() This addresses one issue raised in #1863. register_extension() is only called once, while reset() is called whenever the processor_t is reset. This ensures that extension_t state, including CSRs, is always reset with reset()	1 year ago
Andrew Waterman	7812eabb44	Merge pull request #1862 from NewPaulWalker/fix-hvip Fix WMASK of LCOFI bit(bit 13) in hvip	1 year ago
linzhida	275c668443	Fix WMASK of LCOFI bit(bit 13) in hvip For implementations that support Smcdeleg/Ssccfg, Sscofpmf, Smaia/Ssaia, and the H extension, the LCOFI bit (bit 13) in each of hvip and hvien is implemented and writable.	1 year ago
Andrew Waterman	eb0a3e2b0a	Merge pull request #1860 from XYenChi/master Fix formatting of assembly code within comments	1 year ago
XYenChi	5cc162c482	Fix format	1 year ago
Andrew Waterman	2c67071743	Merge pull request #1859 from ved-rivos/issue_1857 Add missing priv qualification to prev_virt	1 year ago
Ved Shanbhogue	64972b7d9f	Add missing priv qualification to prev_virt	1 year ago
Jerry Zhao	4156e0735a	Merge pull request #1853 from arrv-sc/master feat: add possibility for custom CSRs	1 year ago
Alexander Romanov	adafbd3240	feat: add possibility for custom CSRs Currently in riscv-isa-sim there's no way to make a custom extension that adds new CSRs. This simple patch makes it possible via new virtual function in extension_t class.	1 year ago
Andrew Waterman	fd0a927d5b	Merge pull request #1848 from riscv-software-src/fix-1846 Fix FCSR accesses under Zfinx	1 year ago
Andrew Waterman	1adf60f566	Fix FCSR accesses under Zfinx	1 year ago
Andrew Waterman	ce71e753d3	Remove require_fs macro, as it is only used once	1 year ago
Jerry Zhao	f0d4d42913	Merge pull request #1830 from demin-han/master Fix non-standard interrupt start position	1 year ago
demin.han	2688d179b1	Fix non-standard interrupt start position Signed-off-by: demin.han <demin.han@starfivetech.com>	1 year ago

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3516 Commits (36c40295b47f3deda61fd947983e1ee450485b41) All Branches Search

3516 Commits (36c40295b47f3deda61fd947983e1ee450485b41)

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