Based on spec
section 18.4
"The Zvfhmin extension depends on the Zve32f extension."
section 18.5,
"The Zvfh extension depends on the Zve32f and Zfhmin extensions."
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
In privilege spec sec 3.1.18
" The Ssdbltrp extension adds the double-trap-enable ( DTE ) field in
menvcfg . When menvcfg.DTE is zero, the implementation behaves as
though Ssdbltrp is not implemented. When Ssdbltrp is not implemented
sstatus.SDT , vsstatus.SDT , and henvcfg.DTE bits are read-only zero."
The change keep the mstatus.sdt unchangedable and always read-as-zero
when menvcfg.dte is cleared
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
vfncvtbf16_f_f_w and vfwcvtbf16_f_f_v only depend on
Zvfbf16min but not Zvfbfa
ref:
https://github.com/aswaterman/riscv-misc/blob/main/isa/zvfbfa.adoc
"
vfwcvtbf16.f.f.v † (only if Zvfbfmin is implemented)
vfncvtbf16.f.f.w † (only if Zvfbfmin is implemented)
The instructions marked with † have the same semantics regardless of altfmt
"
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
`pmp_ok` needs to handle misaligned addresses and non-power-of-2 lengths,
so round them before checking the PMPs.
As an optimization, reduce the number of PMP checks based upon the PMP
granularity.
Dataflow through the PC is an ILP bottleneck. Reduce the critical code path
by memoizing the likely next PC.
The first time an instruction is cached, the assumption is that the likely
next PC is on the sequential path. Whenever the instruction is executed and
the next PC was mispredicted, correct it. This does the right thing for
jumps and heavily biased branches. The misprediction penalty is low enough
that doing something smarter for less-biased branches is unprofitable.
If main memory contained an LPAD instruction but the incoherent I$ contained
an unrelated instruction, then the landing-pad MSBs would not have been
checked. Fix by making the I$ coherent with the LPAD when the initial
landing-pad check is performed.
Add --dm-no-abstractauto flag to disable support for the optional abstractauto
register. When disabled, writes to the register are ignored and the internal state
is kept at 0.
Currently, neither riscv-openocd nor openocd support batch reads or writes for debug modules
that don’t implement abstractauto, as both assume every debug module provides
abstractauto support. However, work is underway to remove this dependency.
Chih-Min Chao
Andrew Waterman
Alexander Romanov
steven
Nadime Barhoumi
Zhibo Hong
Ved Shanbhogue
mslijepc
Alexander Romanov