the default vector parameters are defined in configuration time but can
be changed throught command-line option
Signed-off-by: Dave Wen <dave.wen@sifive.com>
1. configure option "--with-varch"
the option defines the default u-arch implementatiton-decided parameter
VLEN: vector register length in bit
SLEN: striping distance in bit
ELEN: max element size in bit
ex: --with-vector=v128:e32:s128
2. add __int128_t type checking
3. add --varch command option and help message
ex: --varch=v512:e64:s512
Signed-off-by: Dave Wen <dave.wen@sifive.com>
* Clean up debug module options.
1. Instead of passing each one a few levels deep, create
debug_module_config_t which contains them all.
2. Rename all those command line options so they start with --dm for
debug module.
3. Add --dm-no-halt-groups to disable halt group support.
* Update changelog.
This is used to make sure that OpenOCD can work on targets that don't
support abstract access to CSR registers. It replaces a simpler hack,
which caused #266.
* Implement hasel/hawindow support.
This should allow simultaneous resume and halt to work.
* Fix anyrunning/anyhalted bits.
* Add --without-hasel argument for testing.
* Make halt/resume times more equal.
Switching threads after every instruction executed in debug mode leads
to a lot of extra instructions being executed on the "other" thread when
both are really supposed to halt/resume near-simultaneously. Fixed that
by adding wfi to debug_rom.S, and implementing it to switch to the other
hart as well as check for JTAG input.
When resuming, write the hart ID to the debug ROM so that the DM knows
which hart actually resumed. (Before simultaneous resume it just assumed
the current one.)
Also got rid of resume symbol in debug_rom.S since it had no purpose.
* Preserve Debug ROM entry points.
* Make sure minstret is correct when wfi happens.
* Add "--log-cache-miss" option to generate a log of cache miss.
- This option must be used with "--ic" and/or "--dc" options
to enable cache simulation.
- This option is useful with "-l" option to understand
which instruction has caused the cache miss.
* Modify log format of cache miss to reduce log size.
Off by default, enabled with --debug-auth.
The protocol is very simple (definitely not secure) to allow debuggers
to test their authentication feature. To authenticate a debugger must:
1. Read authdata
2. Write to authdata the value that it just read, plus 1
* mem_t: Throw an error if zero-sized memory is requested
If for some reason the user requests a memory size of 0 megabytes, print
a useful error message.
* Check for overflow in memory size
If the user passes in a large enough memory size (-m) that the size in
bytes doesn't fit into size_t, catch this error in the make_mems function.
I currently get this disassembly
00004881 jr a7
but if I understand that's incorrect and I want
00004881 li a7, 0
If I'm reading the ISA manual correctly, the disassembler was just wrong
here.
Chih-Min Chao
Tim Newsome
Andrew Waterman
takeoverjp
Jonathan Neuschäfer
Gleb Gagarin
Kito Cheng
Palmer Dabbelt
Wesley W. Terpstra
Andrew Waterman