Andrew Waterman
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32f8b0bbb8
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Update LICENSE copyright date
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9 years ago |
Wesley W. Terpstra
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b04dfe31de
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fdt: move interrupt controller into its own node
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9 years ago |
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Andrew Waterman
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7b396b51a6
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Set badaddr=0 on illegal instruction traps
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9 years ago |
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Andrew Waterman
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8f4fb411b0
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On EBREAK, set badaddr to pc
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9 years ago |
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Andrew Waterman
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a80c695b19
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Separate page faults from physical memory access exceptions
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10 years ago |
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Andrew Waterman
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1fa2174178
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Default to 2 GiB of memory
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10 years ago |
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Andrew Waterman
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e83a032060
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Require little-endian host
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10 years ago |
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Wesley W. Terpstra
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46f1423c65
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riscv: replace rtc device with a real clint implementation
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10 years ago |
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Wesley W. Terpstra
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693fc45eb8
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sim: declare cores as interrupt-controllers for clint
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10 years ago |
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Wesley W. Terpstra
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212d5198cf
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bootrom: set a0 to hartid and a1 to dtb before boot
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10 years ago |
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Wesley W. Terpstra
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0647cce541
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configstring: rename variables to dts
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10 years ago |
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Wesley W. Terpstra
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4c80b12b1a
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riscv: remove dependency on num_cores
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10 years ago |
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Wesley W. Terpstra
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f7a7557273
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bootrom: include compiled dtb
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10 years ago |
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Wesley W. Terpstra
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4198bc7c62
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sim: create DTS instead of config string
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10 years ago |
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Wesley W. Terpstra
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fcd0f3ab3b
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sim: define emulated CPU clock rate to be 1GHz
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10 years ago |
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Wesley W. Terpstra
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c71db7787b
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autoconf: put location of 'dtc' into config.h
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10 years ago |
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Andrew Waterman
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ee80f2851a
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PUM -> SUM; expose MXR to S-mode
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10 years ago |
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Andrew Waterman
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5ed1c1f9de
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Simplify interrupt-stack discipline
f2ed45b179
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10 years ago |
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Andrew Waterman
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17e3ef9618
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Implement mstatus.TW, mstatus.TVM, and mstatus.TSR
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10 years ago |
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Andrew Waterman
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3c8dafeef0
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Don't overload illegal instruction trap in interactive code
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10 years ago |
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Andrew Waterman
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cbaa72d24c
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Sv57 and Sv64 are not spec'd yet
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10 years ago |
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Andrew Waterman
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6db0707687
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New counter enable scheme
https://github.com/riscv/riscv-isa-manual/issues/10
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10 years ago |
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Andrew Waterman
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13639b9c45
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serialize simulator on wfi
This improves simulator perf when a thread is idle, or waiting on HTIF.
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10 years ago |
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Andrew Waterman
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b47e8c0a19
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Take M-mode interrupts over S-mode interrupts
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10 years ago |
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Andrew Waterman
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f478eef851
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permit MMIO loads to MSIP bit
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10 years ago |
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Andrew Waterman
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67cd71d9ec
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Make HW setting of PTE A/D bits optional (by configure arg)
https://github.com/riscv/riscv-isa-manual/issues/14
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10 years ago |
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Andrew Waterman
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eace559960
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Spike uarch needs TLB flush after SPTBR write
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10 years ago |
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Andrew Waterman
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d503765577
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sfence.vm -> sfence.vma
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10 years ago |
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Andrew Waterman
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a30f158300
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Encode VM type in sptbr, not mstatus
https://github.com/riscv/riscv-isa-manual/issues/4
Also, refactor gdbserver code to not duplicate VM decoding logic.
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10 years ago |
Tim Newsome
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daaf28f729
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Merge pull request #83 from bacam/gdb-protocol-fixes
Gdb protocol fixes
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10 years ago |
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Andrew Waterman
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9e012462f5
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Fix interrupt delegation for coprocessors
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10 years ago |
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Andrew Waterman
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6642f8c745
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For FMIN(sNaN, x) and FMIN(qNaN, qNaN), return canonical NaN
Resolves #76
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10 years ago |
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Andrew Waterman
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d392463e5c
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Set xPIE=1 on xRET
Resolves #88.
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10 years ago |
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Andrew Waterman
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e9e30598e0
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Only allow SIP.SSIP to be toggled if the interrupt is delegated
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10 years ago |
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Andrew Waterman
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b387326dbc
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Make SIP.STIP read-only
h/t Ron Minnich
See https://groups.google.com/a/groups.riscv.org/forum/#!topic/isa-dev/JV-Hj3W5Kw8
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10 years ago |
David Craven
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51a0e1e965
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Comply with GNU coding standards.
Currently the DESTDIR variable is not used correctly which leads to
bogus RUNPATH entries.
https://www.gnu.org/prep/standards/html_node/DESTDIR.html
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10 years ago |
Brian Campbell
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f38dcde0d8
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Only read exception flag in gdb register read/write. (#85)
The flag is 32 bits, and if we read 64/128 bits then we get fragments of
S1 too and can accidentally send an error. Fixes #84.
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10 years ago |
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Brian Campbell
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7647707a60
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Fix gdb communication error (#82)
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10 years ago |
Brian Campbell
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71f64bfe4e
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Remove extra gdb protocol responses on register writes
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10 years ago |
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Brian Campbell
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9e3b7bdc5a
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Fix gdb protocol register read of S0
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10 years ago |
Stefan O'Rear
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07ff3f3b0b
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Use correct format codes for reg_t and size_t
Fixes 32-bit build.
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10 years ago |
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Tim Newsome
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7e31f49535
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Fix single stepping over faulting instructions. (#80)
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10 years ago |
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Tim Newsome
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481afc249e
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Reuse the ebreak constants in encoding.h.
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10 years ago |
Andy Wright
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39ee063f47
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Added comments about the modified Duff's Device in execute.cc (#77)
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10 years ago |
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Andrew Waterman
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679d5f5e92
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Fix 32-bit host portability bug
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10 years ago |
Ben Gamari
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3a7393db14
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Ensure that g++ knows it is building a PCH (#75)
It seems that g++ 5.4 doesn't realize that it is building a precompiled
header unless you pass it -x c++-header.
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10 years ago |
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Andrew Waterman
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bf8d2b71bb
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AMOs should always return store faults, not load faults
This commit also factors out the common AMO code into mmu_t.
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10 years ago |
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Tim Newsome
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ecff67fb34
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Make reading/writing fpu regs work.
Temporarily turn them on in mstatus if necessary.
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10 years ago |
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Tim Newsome
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53db924b02
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Minor code cleanup.
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10 years ago |
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Tim Newsome
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0b554a92ff
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Check for exception after register write.
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10 years ago |
