As proposed in #1652, we made the following changes to MMIO device (factory)
plugin API, to mitigate current limitations and facilitate factory reuse.
- removed `sargs` from `device_factory_t`, and introduced a new type alias
`device_factory_sargs_t` to capture `<device_factory_t *, sargs>` pairs,
this is used to instantiate sim_t instances;
- changed the signature of `device_factory_t::generate_fdt` and
`device_factory_t::parse_from_fdt` to take on an extra `sargs` argument,
for instantiating devices with per-device arguments;
- made `device_factory_t` const and potentially resuable across multiple
`sim_t` instances.
RISC-V ISA states (21.1):
"A standard-compatible global encoding can also use standard prefixes
for non-standard extensions if the associated standard extensions are
not included in the global encoding."
Currently all the instructions (either from standard or custom
extensions) are all being inserted into a single std::vector which is
then being sorted. An instruction matching process performs linear
search on that vector. The problem is that when a custom extension uses
the same opcode as standard one (i.e. match and mask are equal to the
standard counterparts) it is undefined which instruction will be picked.
That is because in std::sort "The order of equal elements is not
guaranteed to be preserved". That being said it is impossible to define
custom extension (via customext) that would use the prefix of a disabled
standard extension.
In this change I separate custom and standard extensions in two separate
std::vector's. By default we report an error if they have common
elements (There're an additional processor_t constructor's argument that
skips this check). If this error is disabled during instruction matching
we first trying to find it among custom instructions. If it has been
found the search is stopped and custom instruction is executed,
otherwise we look for it among standard instructions. Overall this
change does not completely fix the problem but at least makes it
possible to use the feature of RISC-V ISA.
LIU Yu
Alexander Romanov