52b3eb9380
rvv: disasm: fix whole load
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
6 years ago
c9da294332
rvv: add reciprocal instructions
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
6 years ago
bfc2bead78
rvv: remove quad instructions
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
6 years ago
cdda51cb0a
rvv: add vrgatherei16.vv
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
6 years ago
effb92a5ec
rvv: add new whole reg load/store instructions
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
6 years ago
4d6086e094
rvv: op: fix amo naming
The original name misses the 'i' in instruction mae
vamoswape8 -> vamoswapei8
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
6 years ago
3784c3f681
rvv: disasm: fix missing vamoorei operands
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
6 years ago
67b7edd027
Remove deprecated decoding of xor x0,x0,x0
Some UCB implementations once used this to represent a pipeline bubble.
But this encoding is reserved for future standard HINT use.
Resolves #503
6 years ago
0ea56186d5
rvv: disasm: fix vwadd.wx operand
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
6 years ago
7ddc065e54
zfh: disasm: add fp16 disasm
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
6 years ago
4135ac9a40
rvv: disasm: fix vfncvt.f.f.w
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
6 years ago
36ebbb068c
rvv: add new explicit eew load/store instructions
1. unit
2. stride
3. index
4. fault-first
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
6 years ago
3035256f1a
rvv: add amo instructions
use --isa=rv64gcv_zvamo to enable it
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
6 years ago
f5983b39c5
rvv: add new singed/unsiged extension instructions
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
6 years ago
fb84a685a8
rvv: extenc VU structure to support 0.9 new fields
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
6 years ago
59aa87bd5d
rvv: op: change funary op
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
6 years ago
ea4010704b
rvv: disasm: add missing .wx format
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
6 years ago
d09689d271
rvv: fp16: support conversion instrucitons
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
6 years ago
fd8a6369fa
rvv: disasm: leave only SEW-bit segment load/store
new features in spec 0.9
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
6 years ago
7b3d88f5de
rvv: add vfslide1[down|up].vf and refine checking rule
1. new features in spec 0.9
2. also fix destination commitlog information for integer comparison
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
6 years ago
a261be3dc6
rvv: add float conversion for rtz variants
new features in spec 0.9
ref:
https://github.com/riscv/riscv-v-spec/issues/352
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
6 years ago
2e60b8b061
Fix immediate signedness in vector disassembly
6 years ago
a1ed3764b0
rvv: add vmv[1248]r.v
simple register copy instructions
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
6 years ago
ca648e6e24
rvv: fix vfwcvt/vfncvt for f32 -> f64 and f64 -> f32
1. fix disam
2. refine checking rule and move them out of loop
3. add missing exception keeping for each element
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
7 years ago
47c0eb64c8
rvv: replace vn suffic by 'w'
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
7 years ago
9b44e1a071
rvv: add load/store whole register instructions
add vl1r.v/vs1r.v
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
7 years ago
fd132e6214
rvv: rename vfncvt suffix and add rod rouding type
1. vfncvt*.v -> vfncvt*.w
2. add vfncvt.rod.f.f.w
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
7 years ago
828c75ca8b
rvv: add quad insn and new vlenb csr
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
7 years ago
c3b28ab3c6
add vaaddu/vasubu/vfncvt.rod.f.f.v to diassembler
7 years ago
a6dfd4e40f
rvv: remove vmford
has been removed in https://github.com/riscv/riscv-v-spec/pull/249
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
7 years ago
bbe881f3c5
Speed up compilation of disasm.cc, especially in clang
7 years ago
d9881d7b68
Fix c.fldsp/c.fsdsp disassembly bug
7 years ago
ec29540ebe
vext.x.v -> vmv.x.s; unary operation encoding changes
83fc27897bfb40ef10f0
7 years ago
db067bbe5b
vmfirst/vmpopc have been renamed to vfirst/vpopc
7 years ago
3d7c842209
rvv: disasm: add v-spec 0.7.1 support
support most of vector instruction except for AMO extension
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
7 years ago
1d66556fca
fix disassembly of c.addi4spn
Resolves #243
8 years ago
fad88d8140
Fix several disassembler bugs
h/t Shane Lardinois
8 years ago
874e55888f
Add some missing RVC instructions to disassembler
8 years ago
8feec3d0a5
Implement Q extension for disassembler ( #153 )
9 years ago
4c286ec230
Fix disassembly of c.li 0
Resolves #152
9 years ago
7f746b7c2f
Correct c.li and c.lui disassembly ( #118 )
I currently get this disassembly
00004881 jr a7
but if I understand that's incorrect and I want
00004881 li a7, 0
If I'm reading the ISA manual correctly, the disassembler was just wrong
here.
9 years ago
115297efff
FMV.X.S/FMV.S.X -> FMV.X.W/FMV.W.X
9 years ago
9b6843b58b
Remove hret instruction
9 years ago
03b8bad375
Disassemble RVC instructions based on XLEN
The interpretation of RVC opcodes depends on XLEN, and the disassembler
always assumed RV32.
h/t Michael Clark
10 years ago
906bbfae48
Minor usability improvements ( #48 )
* spike_main/disasm.cc: Print unknown CSR numbers in hex
* interactive mode: Print "Unknown command" when appropriate
10 years ago
a9c5b05eca
Remove MTIME[CMP]; add RTC device
10 years ago
27e29e69cc
Split ERET into URET, SRET, HRET, MRET
10 years ago
575054bc4e
Update to hopefully final RVC 1.9 encoding
11 years ago
b0f3ed6e3b
more work towards RVC 1.8
11 years ago
3fddbcc0a5
work towards rvc 1.8
11 years ago
Chih-Min Chao
Andrew Waterman
Kito Cheng
Palmer Dabbelt
Andrew Waterman
neuschaefer