Introduce types and macros useful across multiple Zvk sub-extensions,
including Zvbb and Zvbc. Those will be used by upcoming
per-sub-extension commits.
In particular we introduce "Element Group" types and loop macros handling
those element groups. The concept of element group is described in
<https://github.com/riscv/riscv-crypto/blob/master/doc/vector/riscv-crypto-vector-element-groups.adoc>.
Note that the element group access method is not implemented
for WORDS_BIGENDIAN setup. As such, isa_parser.cc is modified to emit
an error when WORDS_BIGENDIAN is defined and extensions using element
groups are enabled.
Signed-off-by: Eric Gouriou <ego@rivosinc.com>
Zvk is the short name for the Vector Cryptography Instruction
Set Extension Specification being defined at
<https://github.com/riscv/riscv-crypto/tree/master/doc/vector>.
This commit adds support for parsing/enabling the Zvk extensions
(Zvbb, Zvbc, Zvkg, Zvkned, Zvknha, Zvknhb, Zvksed, Zvksh, Zvkt)
and the combo extensions (Zvkn, Zvknc, Zvkng, Zvks, Zvksc, Zvksg).
This is an early commit in a series implementing Zvk. No instructions
are actually defined here, only infastructure that will
support the coming extensions.
The encodings for Zvk instructions have some conflicts with Zpn
encodings. This commit marks those Zpn instructions as overlapping,
and adds checks to error out if conflicting extensions are enabled.
Signed-off-by: Eric Gouriou <ego@rivosinc.com>
This passes our developer test suite, when comparing output
(signature) against the SAIL implementation.
If any corner-cases require additional changes after ACT goes
upstream, we can apply an add-on patch.
This implements the Zicond (conditional integer operations) extension,
as of version 1.0-draft-20230120.
The Zicond extension acts as a building block for branchless sequences
including conditional-arithmetic, conditional-logic and
conditional-select/move.
The following instructions constitute Zicond:
- czero.eqz rd, rs1, rs2 => rd = (rs2 == 0) ? 0 : rs1
- czero.nez rd, rs1, rs2 => rd = (rs2 != 0) ? 0 : rs1
See
https://github.com/riscv/riscv-zicond/releases/download/v1.0-draft-20230120/riscv-zicond_1.0-draft-20230120.pdf
for the proposed specification and usage details.
This fixes a bug where --isa=rv64imafdc would fail to set
extension_table['F'] because of the ad hoc manner in which we were
synchronizing max_isa and extension_table.
The main motivation for this is that we want to move the ISA parsing
logic to run before we even construct a simulator. That's probably a
bit nicer if we don't depend on the processor header.
It also means that we can stop depending on processor.h in disasm.cc
or spike_log_parser.cc (both through disasm.h), which feels a bit
cleaner: making sense of an instruction trace shouldn't really require
knowledge of the internal state of a processor.
Atul Khare
Jerry Zhao
Eric Gouriou
Gianluca Guida
Andrew Waterman
Weiwei Li
Philipp Tomsich
Aaron Durbin
i2h2
liweiwei90
YenHaoChen
Mark Fedorov
Rupert Swarbrick