riscv-isa-sim

Commit Graph

Author	SHA1	Message	Date
Chih-Min Chao	2e24763045	vamo: remove from building list Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	3 years ago
Andrew Waterman	b5d13f3605	Merge pull request #1477 from abejgonzalez/patch-1 Update dtm.h with switch_to_* functions	3 years ago
Abraham Gonzalez	c5eee7426d	Update dtm.h with switch_to_* functions Signed-off-by: Abraham Gonzalez <abe.j.gonza@gmail.com>	3 years ago
Andrew Waterman	d1efcdffff	Merge pull request #1473 from riscv-software-src/unavailable Fix behavior of unavailable harts.	3 years ago
Tim Newsome	77e9aaef19	debug: Abstract commands fail on unavailable harts.	3 years ago
Tim Newsome	7613da4d26	debug: Halted harts can also be unavailable.	3 years ago
Andrew Waterman	847fe5d59a	Merge pull request #1471 from mehnadnerd/patch-1 Change disasm for vset{i}vli with reserved vtypes to display the reserved bits	3 years ago
Brendan Sweeney	cf3f787474	Change disasm for vset{i}vli with reserved vtypes to display the reserved bits Currently there is a bug with the disassembly when vsetivli/vsetvli have invalid vtypes (with reserved bits set). Spike correctly detects this and sets vill, but the disassembler integrated into spike ignores those bits being set and prints the instruction as if they weren't. This makes debugging harder, it looks like an otherwise valid vtype was being rejected and can lead down debugging paths like thinking the vector unit is configured incorrectly. This commit changes the behaviour so that if these reserved bits are set, it prints out the hex value of the vtype. This is understood by the assembler. GCC disassembler prints out the decimal value of the vtype in this case, I think that hex value is clearer but I can change it if desired. Signed-off-by: Brendan Sweeney <brs@eecs.berkeley.edu>	3 years ago
Andrew Waterman	67df25aedc	Merge pull request #1458 from YenHaoChen/pr-multiple-icount Hit multiple icount triggers with different actions	3 years ago
YenHaoChen	9bc80f3d09	triggers: fix: not decrease icount.count on firing other icount with action=debug	3 years ago
YenHaoChen	7b3b2e94ad	triggers: refactor: icount: breakdown detect_icount_match() into detect_icount_fire() and detect_icount_decrement()	3 years ago
Andrew Waterman	eb9a55a519	Merge pull request #1453 from riscv-software-src/attempt-to-fix-mac-ci Attempt to fix Mac OS CI	3 years ago
Andrew Waterman	e3e610050d	Attempt to fix Mac OS CI	3 years ago
Andrew Waterman	d2d9d995a9	Merge branch 'viktoryou-master'	3 years ago
viktoryou	3c8320ecd7	fix condition of executing cbo.inval as a flush operation Signed-off-by: viktoryou <143797577+viktoryou@users.noreply.github.com>	3 years ago
Andrew Waterman	5854ab5218	Merge pull request #1446 from chihminchao/bf16-nanboxed-access fix bf16 nanboxed access	3 years ago
Chih-Min Chao	eff6c60498	bf16: handle invalid Nan-boxed accessing assume 0x0000_0000_0000_7d2d at 0x8000_0000 a0 = 0x8000_0000 fld ft0, 0(a0) <- load 0x0000_0000_0000_7d2d to ft0, it is invalid Nanboxed fcvt.s.bf16 ft1, ft0 <- read bf16 from ft0. it should be 0x7fc0 (bf16 QNaN) but not 0x7e00 (f16 QNaN) Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	3 years ago
Andrew Waterman	db20475248	Merge pull request #1434 from dansmathers/master update model_test.h: set_msw/clear_msw/set_mtimer/clear_mtimer	3 years ago
Andrew Waterman	d1680b75de	Merge pull request #1438 from liuyu81/master fdt: Install header files `fdt.h` and `libfdt_env.h` as needed by `libfdt.h`	3 years ago
Andrew Waterman	3bea946db3	Merge pull request #1439 from MarkLai0317/fix-include-error Include cerrno in fesvr/elfloader.cc	3 years ago
Mark Lai	c6e2b703c5	Include cerrno in fesvr/elfloader.cc It caused compile error "use of undeclared identifier 'errno'" at line 26 and 33. I Add #include <cerrno> in fesvr/elfloader.cc to fix error and compile successfully.	3 years ago
LIU Yu	05c10a06a3	Install header files fdt.h and libfdt_env.h as needed by libfdt.h	3 years ago
Andrew Waterman	5a499ef718	Merge pull request #1436 from ved-rivos/hade_to_adue Rename envcfg.HADE to envcfg.ADUE	3 years ago
Ved Shanbhogue	07c2e2bfcb	rename envcfg.HADE to envcfg.ADUE	3 years ago
Dan Smathers	179951a015	Merge pull request #1 from dansmathers/dansmathers-patch-1 update set_msw/clear_msw/set_mtimer/clear_mtimer	3 years ago
Dan Smathers	de8e0588ac	update set_msw/clear_msw/set_mtimer/clear_mtimer Added ifndef to clint addresses instead of hard-coding Added clear_msw and clear mtimer Tested against Sail/isa-sim with new proposed Smclint/Ssclint arch-tests https://github.com/riscv-non-isa/riscv-arch-test/pull/372 Building a baseline of interrupt tests that changes to SAIL/isa-sim can be tested against when other interrupt extensions are added. Signed-off-by: Dan Smathers <dan.smathers@seagate.com>	3 years ago
Andrew Waterman	ec3c9357ec	Merge pull request #1427 from YenHaoChen/pr-textra-sbytemask triggers: fix textra.sbytemask	3 years ago
Andrew Waterman	c59e80e980	Merge pull request #1381 from rivosinc/smcntrpmf_feature Add Smcntrpmf support	3 years ago
Atul Khare	c927773dd1	Add Smcntrpmf functionality If Smcntrpmf is enabled, mcycle / minstret increment only if counting for the privilege level isn't inhibited in mcyclecfg / minstretcfg.	3 years ago
Atul Khare	62178539f8	Add prv_changed / v_changed fields to state This tracks whether the privilege / virtual mode was changed by the execution of the current instruction.	3 years ago
Atul Khare	1c91fd56ba	Regenerate encoding.h	3 years ago
YenHaoChen	63379810b4	triggers: fix textra.sbytemask Ignore corresponding bytes to the scontext and textra.svalue. Cast 0xff to reg_t for the 34-bit textra64.svalue.	3 years ago
Andrew Waterman	60c08b1ea5	Merge pull request #1383 from rivosinc/sscrind_feature Add Smcsrind / Sscsrind support	3 years ago
Scott Johnson	4d0171931c	Merge pull request #1416 from YenHaoChen/pr-xenvcfg-cbie Legalize xenvcfg.CBIE	3 years ago
YenHaoChen	e7e1880111	legalize henvcfg.CBIE The value 2 of henvcfg.CBIE is reserved. This commit legalizes it to 0. Reference: https://github.com/riscv/riscv-CMOs/issues/65	3 years ago
YenHaoChen	7f22022e1a	legalize senvcfg.CBIE The value 2 of senvcfg.CBIE is reserved. This commit legalizes it to 0. Reference: https://github.com/riscv/riscv-CMOs/issues/65	3 years ago
YenHaoChen	f6e7338b26	legalize menvcfg.CBIE The value 2 of menvcfg.CBIE is reserved. This commit legalizes it to 0 by adding a specialized class envcfg_csr_t. Reference: https://github.com/riscv/riscv-CMOs/issues/65	3 years ago
Andrew Waterman	5e375b98d9	Merge pull request #1422 from mbgg/fix-prefix-warning Fix compilation warning in riscv/execute.cc	3 years ago
Jerry Zhao	1b41ed3c48	Merge pull request #1415 from michalt/memt-virtual Make methods of `mem_t` virtual to allow overriding	3 years ago
Matthias Brugger	6bfab0e212	Fix compilation warning in riscv/execute.cc ../riscv/execute.cc: In function ‘void commit_log_print_insn(processor_t*, reg_t, insn_t)’: ../riscv/execute.cc:132:16: warning: ‘prefix’ may be used uninitialized [-Wmaybe-uninitialized] 132 \| fprintf(log_file, " %c%-2d ", prefix, rd); \| ~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../riscv/execute.cc:88:10: note: ‘prefix’ was declared here 88 \| char prefix; \| ^~~~~~	3 years ago
Michal Terepeta	cb01351666	Introduce `abstract_mem_t` to allow custom implementations This change allows to create custom implementations of `abstract_mem_t` and inject them when constructing `sim_t`. The current `mem_t` implementation remains unchanged. Fixes #1408.	3 years ago
Atul Khare	bc5842f945	Add Smcsrind/Sscsrind support This adds the following CSRs: miselect (0x350), mireg (0x351), mireg2/3 (0x352, 0x353), mireg4-6 (0x355 - 0x357), siselect (0x150), sireg (0x151), sireg2/3 (0x152, 0x153), sireg4-6 (0x155 - 0x157), vsiselect (0x250), vsireg (0x251), mireg2/3 (0x252, 0x253), vsireg4-6 (0x255 - 0x257). Presently, attempts to read / write from ireg? registers will fail, and future extensions will provide proxy CSR mappings for the respective ?ireg CSRs.	3 years ago
Atul Khare	a6bc48b95e	Rengenerate encoding.h	3 years ago
Atul Khare	2d80209347	Add Smcsrind/Sscsrind extensions	3 years ago
Andrew Waterman	432c9ee976	Merge pull request #1413 from YenHaoChen/pr-mcontrol-cbo-zero-tval mcontrol/mcontrol6 on CBO	3 years ago
YenHaoChen	8658429647	mcontrol/mcontrol6 triggers on cbo.flush/clean The mcontrol/mcontrol6 store address before has a higher priority over page faults and access faults. Thus, trigger checking should before the translate(). This commit checks all address of the cache block. Reference: Debug spec 1.0, 5.5.3 Cache Operations Reference: CMO spec 1.0.1, 2.5.4 Breakpoint Exceptions and Debug Mode Entry	3 years ago
Andrew Waterman	371353288e	Merge pull request #1419 from poemonsense/fix-fetch-order mmu: fetch instruction bytes in ascending order	3 years ago
Yinan Xu	93aad1d355	mmu: fetch instruction bytes in ascending order Fetching instruction bytes in descending order would result in wrong xtval update values.	3 years ago
YenHaoChen	4aea5a05ad	fix mcontrol's tval on cbo_zero The tval should capture the effective address on an (trigger) exception. Reference: https://github.com/riscv/riscv-CMOs/issues/55	3 years ago
YenHaoChen	faceda27e6	refactor: mcontrol/mcontrol6: extend check_triggers() with tval parameter	3 years ago

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3026 Commits (2e2476304516945da407727d56944672d2b56698) All Branches Search

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