riscv-isa-sim

Commit Graph

Author	SHA1	Message	Date
Jerry Zhao	b47080fea4	Remove --with-priv compile flag	2 years ago
Jerry Zhao	d90e6df9c3	Remove --with-isa compile-time option	2 years ago
Andrew Waterman	2e816f23cb	Merge pull request #1796 from cyyself/tmp_mcountinhibit add support for mcountinhibit CSR	2 years ago
YenHaoChen	d7ded0cf85	Merge pull request #1793 from rtwfroody/native_triggers2 Only implement one solution for native triggers.	2 years ago
Tim Newsome	0703b44b77	Only implement one solution for native triggers. When S-mode is present, use option 1 (disable triggers in M-mode unless MIE is set) from the Debug Spec. When S-mode is not present, use option 2 (implement mte and mpte bits in tcontrol). See discussion in #1777.	2 years ago
Tim Newsome	451a7dcdd7	triggers: Move allow_action() into common_match() They are always called together, and now we get the previous privilege behavior in both.	2 years ago
Tim Newsome	4abd669b3d	Make allow_action() take proc instead of state	2 years ago
Tim Newsome	9c5a20fbdb	Work if tcontrol doesn't exist.	2 years ago
Yangyu Chen	5a6b789855	add support for mcountinhibit CSR We hardwired mcountinihibit to 0 previously. Now, we implemented it. Signed-off-by: Yangyu Chen <cyy@cyyself.name>	2 years ago
Andrew Waterman	cb78f095de	Merge pull request #1797 from YenHaoChen/pr-vector vector: disassemble: Let operand ordering be vd, [vrf]s1, vs2 to vector multiply-add instructions	2 years ago
YenHaoChen	6a1a5db16b	vector: disassemble: Let operand ordering be vd, [vf]s1, vs2 to vector widening floating-point fused multiply-add instructions	2 years ago
YenHaoChen	b47d0baab3	vector: disassemble: Let operand ordering be vd, [vf]s1, vs2 to vector single-width floating-point fused multiply-add instructions	2 years ago
YenHaoChen	7f38a503d0	vector: disassemble: Let operand ordering be vd, [vr]s1, vs2 to vector widening integer multiply-add instructions	2 years ago
YenHaoChen	ff62109211	vector: disassemble: Let operand ordering be vd, [vr]s1, vs2 to vector single-width integer multiply-add instructions	2 years ago
Andrew Waterman	2538c1fb20	Merge pull request #1788 from riscv-software-src/support-larger-addresses Lift restriction on physical-address size	2 years ago
Andrew Waterman	3c5b1bb09e	Merge pull request #1779 from rtwfroody/trigger_timing For mcontrol6, default to BEFORE timing.	2 years ago
Andrew Waterman	3f556d66e2	Merge pull request #1791 from YenHaoChen/pr-pm pointer masking: Always apply sstatus.MXR regardless of effective V	2 years ago
YenHaoChen	84a212e93b	pointer masking: Always apply sstatus.MXR regardless of effective V ISA spec says "Setting MXR at HS-level overrides both VS-stage and G-stage execute-only permissions."	2 years ago
Andrew Waterman	272c149f37	Merge pull request #1789 from YenHaoChen/pr-pm pointer masking: Consider effective v bit instead of current v bit	2 years ago
YenHaoChen	61d277c49c	pointer masking: Consider effective v bit instead of current v bit A previous commit removes the effectiveness of MPRV to MXR. (https://github.com/riscv-software-src/riscv-isa-sim/pull/1784) However, the removal implies the MPRV affects point masking individually, and the MXR should consider the effective v bit.	2 years ago
Jerry Zhao	5029aa7ce8	Merge pull request #1787 from riscv-software-src/fix-cfg-priv	2 years ago
Andrew Waterman	52f045d9ba	Lift restriction on physical-address size It remains true that PTEs can only represent addresses >= 2^56, but there's no need to impose that constraint on untranslated accesses.	2 years ago
Andrew Waterman	16870946ed	Use create_mem_region for legacy -m argument	2 years ago
Andrew Waterman	eb85c33899	Check size_t bounds overflow in create_mem_region	2 years ago
Andrew Waterman	1b33b5426b	Factor out create_mem_region from parse_mem_layout	2 years ago
Andrew Waterman	60f02dd1d8	Merge pull request #1786 from YenHaoChen/pr-mcontrol triggers: Let mcontrol.match be default (0/equal) if maskmax is 0	2 years ago
Jerry Zhao	eb07f100a3	Use cmdline --priv flag when parsing proc configurations from DTB	2 years ago
YenHaoChen	1510a6e461	triggers: Let mcontrol.match be default (0/equal) if maskmax is 0	2 years ago
YenHaoChen	d13dc0b3e3	triggers: mcontrol: refactor: Add mcontrol_t::maskmax	2 years ago
Andrew Waterman	20cd44ade6	Merge pull request #1784 from YenHaoChen/pr-pm pointer masking: Pointer masking does not apply when MXR=1 regardless of MPRV in v1.0.0-rc2	2 years ago
YenHaoChen	71bdc3bbd1	pointer masking: Pointer masking does not apply when MXR=1 regardless of MPRV in v1.0.0-rc2 Reference: https://github.com/riscv/riscv-j-extension/issues/70	2 years ago
Andrew Waterman	1b80449f01	Merge pull request #1783 from riscv-software-src/fix-1782 Fix exception priority for RV32E JAL[R], loads, AMOs	2 years ago
Andrew Waterman	73bc67839a	Fix exception priority for RV32E JAL/JALR	2 years ago
Andrew Waterman	5efbfcbfa4	Fix exception priority for RV32E loads and AMOs	2 years ago
Andrew Waterman	c72eca8687	Refactor insn_template to be more DRY	2 years ago
Tim Newsome	a1506ec006	For mcontrol6, default to BEFORE timing. The existing implementation would end up using AFTER even for instruction execute and data store triggers, which is not desirable.	2 years ago
Andrew Waterman	a8c9d9ccb1	Merge pull request #1771 from rtwfroody/match_mask Fix mcontrol6 mask low/high operations.	2 years ago
Tim Newsome	1a15805b94	Fix mcontrol6 mask low/high operations. I doubt this code was ever tested, and this change isn't tested either, because OpenOCD doesn't use this trigger type. This problem was reported in https://github.com/riscv/riscv-debug-spec/issues/1057	2 years ago
Andrew Waterman	f09b02460e	Merge pull request #1722 from ved-rivos/smdbltrp Add Smdbltrp	2 years ago
Andrew Waterman	33d80b40d6	Merge pull request #1776 from YenHaoChen/pr-pm pointer masking: Fix: Let transformed_addr of fetching be unchanged	2 years ago
YenHaoChen	0648ab40fc	pointer masking: refactor: Use xlen to avoid sketchy, hardcoded number 64	2 years ago
YenHaoChen	38330930da	pointer masking: Fix: Let transformed_addr of fetching be unchanged The transformation does not apply to implicit accesses such as instruction fetches.	2 years ago
Andrew Waterman	bfe9173c28	Merge pull request #1769 from riscv-software-src/b-ordering Fix ordering of B single-letter extension	2 years ago
Jerry Zhao	183a2d0a73	Merge pull request #1770 from YenHaoChen/pr-sim Fix a typo in `f11bd7b` (Support parsing procs fully from DTS)	2 years ago
YenHaoChen	20a508244a	Fix a typo in `f11bd7b511`	2 years ago
Jerry Zhao	9031c7b651	Fix ordering of B single-letter extension The canonical order is IMAFDQLCBKJTPVH Signed-off-by: Jerry Zhao <jerryz123@berkeley.edu>	2 years ago
Andrew Waterman	6f28e4bee5	Merge pull request #1768 from riscv-software-src/commit-log-ordered Use ordered map for commit log	2 years ago
Andrew Waterman	8b05d84ee9	Use ordered map for commit log In general, unordered maps should not be used for iteration, only for lookups. In this case, using an ordered map guarantees that the order in which writes are logged is consistent for a given instruction. Resolves #1499	2 years ago
Andrew Waterman	91793ed7d9	Merge pull request #1764 from ved-rivos/exts Update readme with recently included extensions	2 years ago
Ved Shanbhogue	c302e8bd16	Add Smdbltrp	2 years ago

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3587 Commits (2c26357d0ca33d9a542a6db840f7b72d9d717d5f) All Branches Search

3587 Commits (2c26357d0ca33d9a542a6db840f7b72d9d717d5f)

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