riscv-isa-sim

Commit Graph

Author	SHA1	Message	Date
Andrew Waterman	ac466a21df	Merge pull request #1027 from riscv-software-src/fix-1022 Fix #1022 by removing need to mask insn_t bits	4 years ago
Andrew Waterman	7d943d740a	Don't mask instruction bits No longer needed, since they are no longer sign-extended. Fixes #1022 by eliminating undefined behavior (64-bit instructions resulted in a shift amount equal to the datatype width).	4 years ago
Andrew Waterman	d2020b3256	Zero-extend instructions in spike-dasm ...since we no longer rely on their being sign-extended.	4 years ago
Andrew Waterman	898c0dd6a0	Zero-extend instructions when fetching them from memory ...since we no longer rely on their being sign-extended.	4 years ago
Andrew Waterman	fea4a75d37	insn_t: don't rely on sign-extension of internal encoding	4 years ago
liweiwei90	656fa5acf6	update disasm for cbo.* instructions (#1026 )	4 years ago
Andrew Waterman	caf5a420ef	Remove nonstandard length encoding (#1023 ) This was an artifact of an old P-extension draft that erroneously allocated a reserved major opcode. The newer draft uses a different opcode, so this hack is no longer needed.	4 years ago
Andrew Waterman	901fedb22c	Merge branch 'kwalker27-wfi-cleanup'	4 years ago
Kip Walker	7e9da99668	Remove the now-unused PC_SERIALIZE_WFI When WFI was changed to throw a C++ exception, the special-npc signaling became obsolete.	4 years ago
Andrew Waterman	68b3eb9bf1	Fix RV32 hgatp write mask computation (#1014 ) clang with `-Wall` happened to catch this.	4 years ago
Tim Newsome	a0298a33e7	Move ebreak* logic from take_trap into instructions. (#1006 ) Now that logic only affects ebreak instructions, and does not affect triggers that also cause a trap to be taken. Fixes #725. Although like Paul, I don't have a test for this case. Introduce trap_debug_mode so so ebreak instructions can force entry into debug mode.	4 years ago
Andrew Waterman	32eeb5a2b2	Merge pull request #1003 from vogelpi/include-headers Include recently added headers in riscv/riscv.mk.in	4 years ago
Pirmin Vogel	a59c44eb46	Include recently added headers in riscv/riscv.mk.in	4 years ago
Andrew Waterman	e94d843e8b	Merge pull request #997 from riscv-software-src/simplify-decode_insn Simplify decode_insn and insn_desc_t	4 years ago
Andrew Waterman	78dfe62633	Fix disassembly of custom instructions that overlap standard ones (#999 ) Iterate over the instruction chains in reverse order, prioritizing the last call to `disassembler_t::add_insn`. To preserve behavior for the standard instructions, reverse the order in which we add instructions in the `disassembler_t` constructor. Supersedes #995.	4 years ago
Andrew Waterman	ff645fb4eb	Disassemble Zicbop/Zihintpause HINT instructions (#1000 ) We do not condition them on Zicbop/Zihintpause because, definitionally, all implementations provide them.	4 years ago
Andrew Waterman	918cba10e1	Update README to reflect recently added extensions	4 years ago
Andrew Waterman	500d987d87	Add missing Zicbom and Zicbop extensions to disassembler fallback	4 years ago
Andrew Waterman	2bf4c8c3df	Add missing Q, H, and Svinval extensions to disassembler fallback	4 years ago
Andrew Waterman	e66e2e2b09	Remove now-unnecessary null check from decode_insn Fixes bug introduced in `5b7cdbe1cf`	4 years ago
Andrew Waterman	0676421e93	Assert that nullptrs can't make their way into the instructions list	4 years ago
Andrew Waterman	68b20a9b8a	Remove insn_func_t::supported field The field is rendered unnecessary by `11f5942b7d`. Undoes some changes from `750f008e72`.	4 years ago
Andrew Waterman	11f5942b7d	Don't register instructions that aren't supported These add to the length of the instruction list without providing an apparent benefit.	4 years ago
Andrew Waterman	8ed65cdc51	Merge pull request #992 from rbuchner-aril/rb-pbmte Fix for issue #990, implements the PBMTE bit in the henvcfg /menvcfg reisters	4 years ago
Ryan Buchner	ccfeaa9973	Check for reserved PBMT values during tablewalks and fault if found See #990.	4 years ago
Ryan Buchner	996634f0be	Switch from checking for SVPBMT extension to checking *ENVCFG values during tablewalks Fix issue #990.	4 years ago
Ryan Buchner	ea70a9359d	Add PBMTE bit to menvcfg and henvcfg mask values Also make PBMTE set on reset for backward compatibility. Since before Spike proceeded as if these bits were set if the extension was enabled.	4 years ago
Ryan Buchner	fc35f34fd0	Change henvcfg csr to a henvcfg_csr_t To do so implemented henvcfg_csr_t. henvcfg.PBMTE will be read only 0 if menvcfg.PBMTE = 0.	4 years ago
Andrew Waterman	b19990805f	Merge pull request #994 from chihminchao/rvv-misc-2022-05-11 rvv: fix the checking eew and elen for index load	4 years ago
Chih-Min Chao	08afafccfd	rvv: fix the checking eew and elen for index load eew of index register can't be larger than elen ex: elen = 32, vloxei64.v is illegal Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	4 years ago
Andrew Waterman	3099c33d15	Merge pull request #988 from riscv-software-src/factor-out-macros Factor out P and V extension macros into their own headers	4 years ago
Andrew Waterman	615de147a2	Factor out P extension macros into their own header No functional change.	4 years ago
Andrew Waterman	15a370bde2	Factor out V extension macros into their own header No functional change.	4 years ago
Scott Johnson	8e8af2659a	Merge pull request #983 from soberl/epmp_updates_2 Implement Smepmp extension	4 years ago
soberl	6d2549d2ad	Append smepmp extension 1.0 to the feature list	4 years ago
soberl@nvidia.com	b0fdd88d26	Update pmpaddr_csr_t::access_ok() for ePMP on matching regions	4 years ago
soberl@nvidia.com	115a9b3dc2	Update mmu_t::pmp_ok() for ePMP in case matching region is not found	4 years ago
soberl@nvidia.com	af500657c3	Update csr access rules for ePMP on pmpaddr and pmpcfg	4 years ago
soberl@nvidia.com	84a98f6f71	Implement the new csr mseccfg for ePMP as dummy	4 years ago
Andrew Waterman	89745abd8c	Merge pull request #985 from riscv-software-src/trigger_hit Implement mcontrol.hit bit	4 years ago
Shaked Flur	a8245e92fb	Fix the padding of register names in the log (#987 ) This fix print x5 as "x5 ", instead of "x 5".	4 years ago
jmonesti	8f46a28436	Linking spike_dasm misses libriscv.a dependance (#986 ) Whereas spike-dasm.cc now instanciates an isa_parser_t, the dependance on libriscv.a has become unconditional.	4 years ago
Tim Newsome	62ecca6f8a	Use MCONTROL_TYPE_MATCH macro instead of 2	4 years ago
Tim Newsome	85fbd75d44	Implement mcontrol trigger hit bit.	4 years ago
Andrew Waterman	1df65613df	Add missing description of --dtb in --help message	4 years ago
Yan	1cfffeda1e	Add zknd zkne zknh zksed zksh disassembly support (#979 )	4 years ago
Tim Newsome	f2f6037fea	Remove mcontrol_t.h It was removed from the spec a long time ago.	4 years ago
Scott Johnson	1dbcee7d97	Merge pull request #978 from rbuchner-aril/amo-order-change-patch Bug Fix for bug introduced in PR #976	4 years ago
Tim Newsome	16413646bb	Remove maskmax as a variable.	4 years ago
Tim Newsome	d9131e3b1d	Remove mcontrol_t.type. It's not writable anyway.	4 years ago

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2297 Commits (2a7c33b8b50f91379a12f983dd3c1c7ee9f89a90) All Branches Search

2297 Commits (2a7c33b8b50f91379a12f983dd3c1c7ee9f89a90)

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