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riscv-isa-sim
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6 Commits (29dca8b846250a015e84b36e40f4bd1b57bf55fa)

Author SHA1 Message Date
Schuyler Eldridge b3855682c2 Add missing stdexcept imports
6 years ago
Chih-Min Chao b6f7b65b65 op: update CSR
6 years ago
Andrew Waterman acd953afd2 When enabling the debug module, poll til it's really enabled
6 years ago
Megan Wachs b8eb9cd50d FESVR: ensure dmactive is 1 before reading debug module registers
6 years ago
Megan Wachs 6b90a455dc FESVR: Can't read a DM register when DMACTIVE=0
6 years ago
Andrew Waterman f49618ca9d Add fesvr; only globally install fesvr headers/libs
7 years ago