4022 Commits (276be7383b5c64a6c9b46810f8f930e942ef019b)
 

Author SHA1 Message Date
Andrew Waterman 0f8875631a
Merge pull request #2013 from binno/aia_fix 11 months ago
Binno 5d0ab7e1f0 Check H extension enabled when accessing hvictl 11 months ago
Binno c17d206089 Continue mseccfg write operation even without PMP setting 1 year ago
Binno 46fdf37d65 Adjust vsdeleg from VSSIP to SSIP interrupt occurred 11 months ago
Binno 7c01135f5b Ensure AIA extension enabled when accessing hvictl 12 months ago
Andrew Waterman 065950a045
Merge pull request #2010 from jmonesti/perf.aia 11 months ago
Jean-François Monestier 4dfba258d9 Performance: processor_t::take_interrupt() should check EXT_SSAIA 11 months ago
Andrew Waterman 5cb0a97677
Merge pull request #2008 from HaochenGui/all-one-agnostic 11 months ago
Haochen Gui 1ec477fffe Bypass masked-off elements for viota 11 months ago
Andrew Waterman 4f1d8abf39
Merge pull request #2005 from riscv-software-src/ziccid 11 months ago
Andrew Waterman 833ab91894 Reduce perf impact of Ziccid 11 months ago
Andrew Waterman cce834e437 Support Ziccid extension 11 months ago
Andrew Waterman b6a061b683 Support Ziccif extension 11 months ago
Andrew Waterman 99194302df
Merge pull request #2004 from jmonesti/bugfix-cm.jalt 11 months ago
Jean-François Monestier 2554792041 Bugfix cm.jalt 11 months ago
Andrew Waterman 5894afaaa5
Merge pull request #2001 from Steven-Li-Xiaogang/master 11 months ago
steven 937e812212 menvcfg.CDE is defined by Smcdeleg 11 months ago
Andrew Waterman 4c870d063d
Merge pull request #1998 from mingtians/update-readme 12 months ago
mingtians 05f2a66564 Update README with Zimop extension 12 months ago
Andrew Waterman d28344a1e7
Merge pull request #1988 from binno/pr-aia 12 months ago
Andrew Waterman a3dbcbadf3
Merge pull request #1997 from riscv-software-src/fix-1996 12 months ago
Andrew Waterman 37db712878 Partially revert #1987 to fix regrssion in vsra.vi and vssra.vi 1 year ago
Andrew Waterman c8b8821eac Fix unused variable warnings 12 months ago
Andrew Waterman a07c190ed6
Merge pull request #1995 from arrv-sc/arrv-sc/fix-store-segfault 12 months ago
Alexander Romanov 7d43d38e4a fix: log store only if it actually happened 1 year ago
Andrew Waterman 14cad996bf
Merge pull request #1993 from arrv-sc/arrv-sc/init-blocksz 1 year ago
Mladen Slijepcevic f6b16b1b3c
Merge pull request #1990 from mslijepc/mslijepc_20250514_external-sim-ptr 1 year ago
mslijepc 5bf00a87f9 minor spacing fix 1 year ago
Alexander Romanov b346571e35 feat: move cache block size initialization to constructor 1 year ago
Andrew Waterman cb74be07d0
Merge pull request #1888 from tsewei-lin/vector-crypto-misaligned 1 year ago
Andrew Waterman 615e47dfc8
Merge pull request #1991 from arrv-sc/arrv-sc/const-get-isa 1 year ago
Andrew Waterman 7a16d71ccf
Merge pull request #1992 from arrv-sc/arrv-sc/init-xlen 1 year ago
Jerry Zhao 587cf70f4f
Merge pull request #1989 from tianrui-wei/tianrui/decode_opcode 1 year ago
tsewei-lin 7347f43f45 vector: crypto: fix EMUL alignment check for .vs operations 1 year ago
tsewei-lin 789068f8cd vector: crypto: fix overlap check when EGW > VLEN 1 year ago
tsewei-lin b30b11dfef vector: crypto: fix constraint checks for vector-crypto instructions 2 years ago
Alexander Romanov 1e56ecb6a0 feat: initialize xlen in constructor 1 year ago
Alexander Romanov 94147851a0 feat: mark processor_t getters as const 1 year ago
Mladen Slijepcevic 80084a8ae3
Merge branch 'riscv-software-src:master' into mslijepc_20250514_external-sim-ptr 1 year ago
mslijepc 40d9232e8e changing type of external_simulator member of external_sim_device_t 1 year ago
Binno 46acb4f8fa Fix typo for implementation of AIA extension 1 year ago
Binno 9271036d27 Register hidelegh csr with aia_rv32_high_csr_t class 1 year ago
Binno f874622b21 Modify non-standard interrupt start position 1 year ago
YenHaoChen 50a4aff9b8 AIA: Raise virtual instruction exception on writing stimecmp (stimecmph) from VS-mode when hvictl.VTI=1 2 years ago
YenHaoChen 45166a8cd4 AIA: Raise virtual instruction exception on acessing sie or sip (sieh or siph) from VS-mode when hvictl.VTI=1 2 years ago
YenHaoChen acf8dace9f Smstateen: Implement *stateen0[59] controlling RV32-only CSRs (v)siph, (v)sieh, hidelegh, and hviph 2 years ago
YenHaoChen ae557fd260 Smstateen: Implement *stateen0[59] controlling CSR stopi 2 years ago
YenHaoChen 9bee68e28b Smstateen: Implement *stateen0[59] controlling CSR vstopi 2 years ago
YenHaoChen cbf9a1c166 Smstateen: Implement *stateen0[59] controlling CSRs hvien(h), hvictl, hviprio[12](h), and supervisor-level iprio array 2 years ago
YenHaoChen 2817c84bd9 Smstateen: Implement *stateen0[60] controlling CSRs (v)siselect and (v)sireg 2 years ago