Tree: 276be7383b

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Commit Graph

4022 Commits (276be7383b5c64a6c9b46810f8f930e942ef019b)

 

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Author	SHA1	Message	Date
Andrew Waterman	11ee6d0300	Merge pull request #2105 from fk-sc/fk-sc/configurable-datacount Add configurable datacount for debug module	7 months ago
Andrew Waterman	9b136d0210	Merge pull request #2103 from riscv-software-src/fix-func-decl fix: move vectorUnit_t::elt defintion to the header	7 months ago
Farid Khaydari	5397899bb9	Add configurable datacount for debug module This commit adds support for configuring the number of data registers available in the debug module. Previously, the debug module had a fixed datasize of 2, but now users can specify the number of data registers using the --dm-datacount option when running spike. The changes include: - Adding a datacount parameter to debug_module_config_t - Making dmdata a std::vector instead of a fixed array - Validating that datacount is between 1 and 12 - Updating the debug module to use the configured datacount - Adding command-line option to set datacount - Updating documentation in help output Signed-off-by: Farid Khaydari <f.khaydari@syntacore.com>	7 months ago
Alexander Romanov	d018cabce3	fix: move vectorUnit_t::elt defintion to the header Prior to this commit vectorUnit_t::elt was a bottleneck for vector instructions performance. This function was not being inlined because the definition was inside a .cc file. After moving the definition to the header file I measured the 20-30% increase in performance on random vector test from CI.	7 months ago
Andrew Waterman	8df626bf1d	Merge pull request #2099 from riscv-software-src/vector-tests test: add basic random tests for V extension	7 months ago
Alexander Romanov	dac31c1799	test: add basic random tests for V extension	7 months ago
Andrew Waterman	4d6c71e327	Merge pull request #2095 from arrv-sc/arrv-sc/snippy-tests ci: add testing with llvm-snippy	7 months ago
Alexander Romanov	c44fd213bd	ci: add testing with llvm-snippy This commits adds basic spike testing using llvm-snippy random code generator. This initial testing runs spike on random valid code snippets and checks that it doesn't fail. Co-authored-by: Ksenia Dobrovolskaya <ksenia.dobrovolskaya@syntacore.com>	8 months ago
Andrew Waterman	fe57ec514d	Merge pull request #2096 from riscv-software-src/remove-ci-tarball Remove CI tarball; build tests in CI	8 months ago
Andrew Waterman	e360efb8d1	Build tests in CI rather than downloading a tarball from github	8 months ago
Andrew Waterman	38eec3f323	Merge pull request #2097 from riscv-software-src/fix-werror Actually use -Werror in CI again	8 months ago
Andrew Waterman	e2eb763332	Add ci-tests/.gitignore	8 months ago
Andrew Waterman	4a429d146d	Install cross compiler package	8 months ago
Andrew Waterman	ffcc3e69a7	Actually use -Werror in CI again	8 months ago
Andrew Waterman	e69c5376a5	Suppress warning for unused write() result	8 months ago
Andrew Waterman	9ea67d0ca8	Add UNUSED to suppress warning	8 months ago
Andrew Waterman	eb90f5aa75	Add default destructor to suppress warning	8 months ago
Andrew Waterman	837fcf7c15	Avoid VLAs	8 months ago
Andrew Waterman	9145cdcae2	Merge pull request #2094 from chihminchao/enhance-amo-disasm disasm: show the acquire and release attribute to amo instructions	8 months ago
Andrew Waterman	bccbf3b3de	Merge pull request #2093 from chihminchao/ext-zibi new extension : zibi	8 months ago
Andrew Waterman	aee4555eea	Merge pull request #2092 from riscv-software-src/zvfqbdot8f Implement Zvfqbdot8f and Zvfqldot8f	8 months ago
Chih-Min Chao	7b060d0d86	disasm: show the acquire and release attribute to amo instructions Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	8 months ago
Chih-Min Chao	e2e02098a4	ext: add zibi It implement v0.6 version reference https://github.com/riscv/zibi/releases/download/v0.6/zibi.pdf https://riscv.atlassian.net/wiki/spaces/USXX/pages/599261201/Branch+with+Immediate+Zibi+Ratification+Plan Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	8 months ago
Chih-Min Chao	4c6be8305c	update encoding.h Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	8 months ago
Andrew Waterman	3232ce1b76	Implement Zvflqdot8f	8 months ago
Andrew Waterman	e3dc14a878	Implement Zvfbqdot8f	8 months ago
Andrew Waterman	a07e44071f	Use bulk normalization algorithm for Zvfqbdot8f	8 months ago
Andrew Waterman	3b066d68fe	Merge pull request #2089 from chihminchao/fix-mseccfg-rv32 csr: fix mseccfg for rv32	8 months ago
Andrew Waterman	b3b7ed4c36	Merge pull request #2091 from aap-sc/aap-sc/leakage_fix Get rid of leaking pointers in examples for custom extension	8 months ago
Parshintsev Anatoly	a191144b7a	Get rid of leaking pointers in examples for custom extention Building of spike-based simulator with memory sanitizer reports leaking pointers if custom extension are used. This is because existing facilities do not have a proper destructor procedure, so the objects representing custom extentions are leaked. This commit implements quick-and-dirty fix for the problem.	8 months ago
Chih-Min Chao	180c10fe42	csr: fix mseccfg for rv32 Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	8 months ago
Andrew Waterman	bfe100fbd3	Merge pull request #2088 from ved-rivos/issue_2078 PTE store in s2xlate should use the trap_type instead of type	8 months ago
Ved Shanbhogue	cfd4930cb6	PTE store in s2xlate should use the trap_type instead of type	8 months ago
Andrew Waterman	f51df5d395	Merge pull request #2077 from riscv-software-src/fix-2076 Prevent div-by-0 when executing Zvbdot instructions with VLEN=0	8 months ago
Andrew Waterman	18bcac3d94	Prevent div-by-0 when executing Zvbdot instructions with VLEN=0 Fixes #2076	8 months ago
Andrew Waterman	545712a6f7	Merge pull request #2074 from riscv-software-src/fix-2073 Allow DEBUG_START to be nonzero again	8 months ago
Andrew Waterman	e80b890ebf	Suppress -Wtype-limits warning	8 months ago
Andrew Waterman	3d85f9af29	Merge pull request #2072 from ved-rivos/issue_2063 Clear SDT in the temporary state variable	8 months ago
Ved Shanbhogue	743732c3e6	Clear SDT in the temporary state variable	8 months ago
Andrew Waterman	d3be9a4d9d	Merge pull request #2069 from riscv-software-src/fix-zve Relax VLEN/ELEN checking	8 months ago
Andrew Waterman	1d56b556b5	Relax VLEN/ELEN checking We should allow ISA strings like rv64gc_zve32f. Per the spec, the various Zve extensions imply a minimum VLEN, so rv64gc_zve32f is unambiguously equivalent to rv64gc_zve32f_zvl32b. Similarly, rv64gc_zve64x, rv64gc_zve64x_zvl64b, and rv64gc_zve64x_zvl32b are all unambiguously equivalent.	8 months ago
Andrew Waterman	faeae4eada	VLEN is unitless	8 months ago
Andrew Waterman	acac77d59d	No tabs	8 months ago
Andrew Waterman	c3ec317126	Merge pull request #2066 from riscv-software-src/quiet-ci Quiet the CI logs	8 months ago
Andrew Waterman	7e389e824f	Quiet the CI logs Send instruction traces to /dev/null to make the CI logs readable.	8 months ago
Andrew Waterman	19409bdfac	Merge pull request #2065 from riscv-software-src/ldot Add Zvldot extension support	8 months ago
Andrew Waterman	dcef3e5881	Merge pull request #2054 from nadime15/update_vlen_elen Add VLEN >= ELEN validation check	8 months ago
Andrew Waterman	717a6e275c	Add Zvldot extension support	8 months ago
Andrew Waterman	cfc472e83b	Use f32_add_bulknorm_odd for vfwbdot	8 months ago
Andrew Waterman	cf7d57ef74	Add f32_add_bulknorm_odd routine Used by Zvldot/Zvbdot	8 months ago