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riscv-isa-sim
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952 Commits (2710fe575e7e6a4e2418224f8d254d5ca31f6c0e)
 

Author SHA1 Message Date
Wesley W. Terpstra 46f1423c65 riscv: replace rtc device with a real clint implementation
10 years ago
Wesley W. Terpstra 693fc45eb8 sim: declare cores as interrupt-controllers for clint
10 years ago
Wesley W. Terpstra 212d5198cf bootrom: set a0 to hartid and a1 to dtb before boot
10 years ago
Wesley W. Terpstra 0647cce541 configstring: rename variables to dts
10 years ago
Wesley W. Terpstra 4c80b12b1a riscv: remove dependency on num_cores
10 years ago
Wesley W. Terpstra f7a7557273 bootrom: include compiled dtb
10 years ago
Wesley W. Terpstra 4198bc7c62 sim: create DTS instead of config string
10 years ago
Wesley W. Terpstra fcd0f3ab3b sim: define emulated CPU clock rate to be 1GHz
10 years ago
Wesley W. Terpstra c71db7787b autoconf: put location of 'dtc' into config.h
10 years ago
Palmer Dabbelt 773fab34d4 spec bump
10 years ago
Andrew Waterman ee80f2851a PUM -> SUM; expose MXR to S-mode
10 years ago
Andrew Waterman 5ed1c1f9de Simplify interrupt-stack discipline
10 years ago
Andrew Waterman 17e3ef9618 Implement mstatus.TW, mstatus.TVM, and mstatus.TSR
10 years ago
Andrew Waterman 3c8dafeef0 Don't overload illegal instruction trap in interactive code
10 years ago
Andrew Waterman cbaa72d24c Sv57 and Sv64 are not spec'd yet
10 years ago
Andrew Waterman 6db0707687 New counter enable scheme
10 years ago
Tim Newsome ab8a5631c3 Update bits to latest spec.
10 years ago
Tim Newsome 5a9e289624 Implement halt request.
10 years ago
Tim Newsome 21fb735d62 Improve debug performance.
10 years ago
Tim Newsome 0e848d2f43 Don't waste time spinning in place in debug mode
10 years ago
Andrew Waterman 13639b9c45 serialize simulator on wfi
10 years ago
Andrew Waterman b47e8c0a19 Take M-mode interrupts over S-mode interrupts
10 years ago
Andrew Waterman f478eef851 permit MMIO loads to MSIP bit
10 years ago
Andrew Waterman 67cd71d9ec Make HW setting of PTE A/D bits optional (by configure arg)
10 years ago
Andrew Waterman eace559960 Spike uarch needs TLB flush after SPTBR write
10 years ago
Tim Newsome e36bacd9bc Compress log output of jump-to-self loops.
10 years ago
Tim Newsome 8c19757cf5 Remove noisy debugs.
10 years ago
Tim Newsome 8dd673b744 Set cmderr when data is accessed while busy.
10 years ago
Tim Newsome f88504000a Implement autoexec. DMI op 2 is just write now.
10 years ago
Tim Newsome 4df7f6d279 Implement resume (untested).
10 years ago
Andrew Waterman d503765577 sfence.vm -> sfence.vma
10 years ago
Tim Newsome 294a0572c4 Implement program buffer preexec/postexec.
10 years ago
Tim Newsome ae67cde583 dbus -> dmi
10 years ago
Tim Newsome 1a62370146 Abstract register read mostly working.
10 years ago
Tim Newsome f7f1105040 Fix stack overflow and support --rbb-port=0
10 years ago
Tim Newsome b4de20a92e Entering debug mode now jumps to "dynamic rom"
10 years ago
Tim Newsome 8a09a059dc Implement hartstatus field.
10 years ago
Tim Newsome a62a819679 Remove gdbserver support.
10 years ago
Tim Newsome c704a804ba Add writable ibuf and data registers.
10 years ago
Tim Newsome 4845819872 Serve up a correct dmcontrol register.
10 years ago
Andrew Waterman a30f158300 Encode VM type in sptbr, not mstatus
10 years ago
Tim Newsome 94277648d5 OpenOCD does a dmi read and gets dummy value back.
10 years ago
Tim Newsome daaf28f729 Merge pull request #83 from bacam/gdb-protocol-fixes
10 years ago
Tim Newsome 1f65ba49ea Remove unnecessary circular buffer code.
10 years ago
Tim Newsome 4695be7cea Refactor remote bitbang code.
10 years ago
Tim Newsome 9be1570420 OpenOCD RISC-V code now gets to scan out dtmcontrol.
10 years ago
Tim Newsome f6a7fe2c4e OpenOCD can now scan out the hacked IDCODE.
10 years ago
Tim Newsome d1f2cf337e OpenOCD connects, and sends some data that we receive.
10 years ago
Andrew Waterman 9e012462f5 Fix interrupt delegation for coprocessors
10 years ago
Andrew Waterman 6642f8c745 For FMIN(sNaN, x) and FMIN(qNaN, qNaN), return canonical NaN
10 years ago