riscv-isa-sim

Commit Graph

Author	SHA1	Message	Date
Jerin Joy	204a639780	Build and install lib and header dependencies for Hammer https://github.com/rivosinc/hammer Signed-off-by: Jerin Joy <joy@rivosinc.com>	4 years ago
Andrew Waterman	2a7c33b8b5	Merge pull request #1088 from riscv-software-src/werror Run CI with -Werror	4 years ago
Andrew Waterman	7cf82d72f1	Run CI with -Werror	4 years ago
Andrew Waterman	c2a47571be	Propagate CFLAGS passed to configure into CXXFLAGS	4 years ago
Andrew Waterman	7c4cf010a1	Merge pull request #1085 from ImanHosseini/patch1 Detect loading isa-incompatible code	4 years ago
Andrew Waterman	326fa00f58	Merge pull request #1036 from plctlab/plct-sscofpmf-dev add support for sscofpmf extension v0.5.2	4 years ago
Iman Hosseini	dfd1913679	detects the loading of isa-incompatible (i.e. 32 bit code to 64bit HART) code and emits an error message to help avoid unintentionally loading wrong elf.	4 years ago
YenHaoChen	ccc9791807	Fix trigger never fire on executing an instruction on plugin devices (#1084 ) The trigger matching only checks on TLB hit (after refill_tlb()). However, instructions on plugin devices will never be filled into the TLB; thus, triggers cannot fire when executing instructions on the plugin devices. The PR removes the if-condition of TLB hit for trigger checking. Co-authored-by: Howard Yen-Hao Chen <yhchen@andestech.com>	4 years ago
Scott Johnson	1fd6f53f5b	Merge pull request #1086 from scottj97/use-default-inits Initialize triggers using default member initializers	4 years ago
Scott Johnson	95f36bc28e	Initialize triggers using default member initializers Instead of constructor member initializer lists, which require repeating the list of members, and cause ugly merge conflicts when the list of members changes.	4 years ago
Scott Johnson	a0972c82d0	Merge pull request #1080 from scottj97/trigger-cleanup Remove obsolete enum trigger_operation_t	4 years ago
Andrew Waterman	0654e4f75a	Merge pull request #1081 from plctlab/plct-nonfunc-for-rvv Non-functional changes for RVV	4 years ago
Scott Johnson	711215124b	Remove obsolete enum trigger_operation_t Moved to triggers.h and renamed in `a2a2587426`, but the old enum was mistakenly left behind.	4 years ago
Weiwei Li	25bca65b95	Remove redundant require_vm in macro VI_VV_LOOP_WITH_CARRY and VI_XI_LOOP_WITH_CARRY: require_vm is also included in VI_CHECK_SSS	4 years ago
Weiwei Li	d85446f81f	Remove unnecessary argument alu(always false) from macro require_vector_novtype	4 years ago
Weiwei Li	3721abe667	Remove redundant require_vector in macro VI_MERGE_LOOP_BASE require_vector is also included in VI_GENERAL_LOOP_BASE	4 years ago
Andrew Waterman	2437a717c8	Merge pull request #1079 from riscv-software-src/fix-vmvnfr vmv<nf>r.v depends on vtype, and therefore should check vill	4 years ago
Andrew Waterman	503b0106d7	fix comment in definition of vmv<nf>r.v	4 years ago
Andrew Waterman	4d515ade6e	vmv<nf>r.v depends on vtype, and therefore should check vill	4 years ago
Andrew Waterman	476a79fe2f	Substantially increase context_t stack size It's nearly free to do so, because it's just virtual address space. @davidbiancolin recently fell into this pit when using context_t with VCS.	4 years ago
Kip Walker	204f43cf82	Add disassembly support for Zbc instructions (#1076 )	4 years ago
Scott Johnson	7f2f73609b	Merge pull request #1074 from YenHaoChen/master Fix tval on illegal instruction faults with long illegal instruction	4 years ago
Rupert Swarbrick	f1c5178f2c	Fix libdir and includedir in pkg-config files (#917 ) The autoconf @libdir@ and @includedir@ variables include the prefix part so we were generating things like "/usr//usr/lib".	4 years ago
YenHaoChen	3ac734e195	Fix tval on illegal instruction faults with long illegal instruction The current spike implementation does not include the ILEN (maximum instruction length supported by the implementation), which is required to constrain the value of tval on an illegal instruction exception. Consider an implementation supporting only an RV64I base instruction set. The ILEN is 32 bits (spec sec. 1.5), and the MXLEN is 64 bits (spec sec. 5.1). Under an illegal instruction exception with the instruction longer than the ILEN, the mtval should contain the first ILEN (32 bits) of the faulting instruction. However, the current spike implementation lets the mtval be the instruction's first MXLEN (64 bits). To fix this bug, this PR masks out the upper bits of the tval and leaves the first ILEN bits of the faulting instruction. When this PR is being made, all official instructions are either 16 or 32 bits. So, We hard- code the ILEN to 32 bits.	4 years ago
Andrew Waterman	07b30ea4f4	Merge pull request #1073 from scottj97/rename-paddr Rename misleading variable	4 years ago
Scott Johnson	d3cb247051	Constantize variables Because it's always better to do so where possible.	4 years ago
Scott Johnson	2667f611fb	Separate variables that contain two different things No reason to use a variable misleadingly named 'paddr' to hold the virtual address.	4 years ago
yangcheng	1556cf7fe2	Fix redundant loops when calculating vrgather.vi. (#1072 )	4 years ago
Andrew Waterman	25f2e61d0e	"Implement" Zihintntl extension (#1071 ) These are just HINTs, so Spike only needs ISA-parser support.	4 years ago
ksco	6aa46e99c3	Remove unused code in vsmul* (#1069 )	4 years ago
Greg Chadwick	ac117cc35a	Unify PMPCFGx behaviour with PMPADDRx where PMP is disabled (#1068 ) Previously any access to the PMPADDRx CSRs when no PMP regions were configured would result in an illegal instruction trap, whilst PMPCFGx registers would act as WARL, ignoring writes and reading as 0. This unifies the behaviour so both PMPADDRx and PMPCFGx CSRs produce an illegal instruction trap when accessed when no PMP regions are configured.	4 years ago
ksco	f04675c96c	Remove dead code in VI_VV_EXT macro (#1065 )	4 years ago
Andrew Waterman	6dcef28ed2	Merge pull request #1066 from plctlab/plct-nonfunc-fix Fix some non-functional problems	4 years ago
Weiwei Li	ce34edb0ee	Add space between if/while/switch and '(' Add space between ')' and '{'	4 years ago
Weiwei Li	2aaa89c0cf	Improve write log for vtype in set_vl Two writes to vtype will be logged in commitlog if vill is true	4 years ago
Weiwei Li	793ffe508a	Fix code indentation in processor.cc, interactive.cc, debug_module.h/cc execute.cc, entropy_source.h and v_ext_macros.h	4 years ago
Weiwei Li	db24e31569	Add missed decription for log-commits option	4 years ago
Weiwei Li	3bbce45031	Fix description for mem related interactive commands Add missed description for untiln interactive commands	4 years ago
Weiwei Li	6b28c78b2c	Add #ifdef RISCV_ENABLE_COMMITLOG for commitlog related code	4 years ago
liweiwei90	7383118078	Fix exception type for accessing (v)stimecmp (#1061 ) Illegal instruciton trap should be raised when accessing if related bit of mcounteren.TM or menvcfg.STCE is zero in VS/VU mode	4 years ago
Weiwei Li	32e199cce4	update README.md	4 years ago
Weiwei Li	6cca5ec9c5	modify take_interrupt to support LCOFIP irq	4 years ago
Weiwei Li	ba10686fd1	add support for sscofpmf extension v0.5.2 since spike doesn't truly support counting of hardware performance events, only csr related read/write functions is supported currently	4 years ago
Andrew Waterman	c5fc01694d	Merge pull request #831 from plctlab/plct-upstream-zfinx add support for zfinx v1.0	4 years ago
Andrew Waterman	dd9bf0d3de	Merge pull request #1059 from plctlab/plct-stateen-fix add stateen related check to frm/fflags	4 years ago
Weiwei Li	caee7f3fa5	Add stateen related check for float point instructions	4 years ago
liweiwei	8aaae32d1d	Add support for freg command to read X regs when enable Zfinx Update README	5 years ago
liweiwei	5de0c89c03	Modify F/D/Zfh instructions to add support for Zfinx/Zdinx/Zhinx{min} instructions change the extention check for F/D/Zfh instructions modify the F/D/Zfh instructions to read X regs when enable Zfinx Co-authored-by: wangmeng <shusheng8495@hotmail.com>	5 years ago
liweiwei	7812b01154	Add flags for Zfinx/Zdinx/Zhinx{min} Hardwire mstatus_fs to zero when enable ZFinx	5 years ago
i2h2	5672c4a41a	Add Sstc support. (#1057 )	4 years ago

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2298 Commits (204a639780dda374320a4ef31d714694db7ae46f) All Branches Search

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