riscv
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riscv-isa-sim
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337 Commits
54 Branches
3 Tags
19 MiB
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Commit Graph

2 Commits (1ea07ef7c5e7f6cee815bb77c8be8487b6598889)

Author SHA1 Message Date
Andrew Waterman 2c1ddd1781 Enable runtime loading of dynamic library with --extlib
12 years ago
Andrew Waterman fb3be24671 Eliminate hwacha <-> riscv circular dependence
12 years ago
Andrew Waterman d5204838b7 Pass target machine's return code back to OS
13 years ago
Yunsup Lee 2f1f9a4fbc revamp hwacha; now runs in physical mode
13 years ago
Andrew Waterman bbb0f2179c Implement RoCC and add a dummy RoCC
13 years ago
Andrew Waterman a68c33c2a4 Add xspike program
13 years ago
Andrew Waterman 790db6c910 Exit cleanly from debug console
13 years ago
Yunsup Lee a9d1c3de84 change riscv-isa-run to spike in documentation
13 years ago
Yunsup Lee b3f7c6045c change riscv-isa-run to spike
13 years ago
Andrew Waterman 28ac3dbd81 add BSD license
13 years ago
Andrew Waterman 290c702c0f specialize fully-associative caches
13 years ago
Andrew Waterman b119073ab0 add I$/D$/L2$ simulators
13 years ago
Andrew Waterman de5b42e923 change htif to link against libfesvr
13 years ago
Andrew Waterman 6405097bf2 remove debug printf
14 years ago
Andrew Waterman 23688da201 poll HTIF occasionally
14 years ago
Rimas Avizienis 91edaf151d added #include <stdlib.h> to get rid of errors building with gcc-4.4 on ubuntu
15 years ago
Andrew Waterman 77452a26e7 temporary undoing of renaming
15 years ago
Andrew Waterman 740f981cfd [sim] renamed to riscv-isa-run
15 years ago
Andrew Waterman d6fd350f0c [xcc] cleaned up mmu code
15 years ago
Andrew Waterman 46f2fb1d9e [sim] hacked in a dcache simulator
15 years ago
Andrew Waterman 481c9e8fd8 [sim] added icache simulator (disabled by default)
15 years ago
Yunsup Lee 133806b398 [sim] various fixes to get the sim work with the fesvr
16 years ago
Andrew Waterman d2c5b5c159 [pk,sim] first cut of appserver communication link
16 years ago
Andrew Waterman 01c01cc36f Reorganized directory structure
16 years ago