riscv-isa-sim

Commit Graph

Author	SHA1	Message	Date
Yang Hau	a41954235b	fix typos	2 years ago
Andrew Waterman	1cf354f9c9	Merge pull request #1823 from YenHaoChen/pr-halt Change -H flag into --halted	2 years ago
Andrew Waterman	382a52638f	Merge pull request #1826 from riscv-software-src/fix-1825 Fix f64_to_bf16 raising underflow when it shouldn't	2 years ago
YenHaoChen	aadd792d6a	Change -H flag into --halted There is a comment about aiming at --halted but failing to achieve so. This commit provides the behavior.	2 years ago
Andrew Waterman	c3f324ff56	Fix f64_to_bf16 raising underflow when it shouldn't Resolves #1825	2 years ago
Andrew Waterman	c95a2cbd68	Merge pull request #1819 from riscv-software-src/ss-cbo-fault Raise store/AMO access fault on CBO to shadow-stack page	2 years ago
Andrew Waterman	00cf1eb2a8	Merge pull request #1820 from YenHaoChen/pr-halt refactor: Remove dcsr::halt variable	2 years ago
YenHaoChen	5c814c7134	refactor: Merge halt and halt_on_reset variables in processor_t	2 years ago
YenHaoChen	871d9453eb	refactor: Move halt out of dcsr Suggested in https://github.com/riscv-software-src/riscv-isa-sim/pull/1816#pullrequestreview-2331806142.	2 years ago
Andrew Waterman	d30dc8e43b	Raise store/AMO access fault on CBO to shadow-stack page Proliferating the access_flags isn't ideal, but it wasn't clear how better to handle this case.	2 years ago
Andrew Waterman	666da337f8	Merge pull request #1816 from YenHaoChen/pr-halt Only enter debug mode once with -H flag (halt_on_reset)	2 years ago
YenHaoChen	6f05a29995	Only enter debug mode once with -H flag (halt_on_reset)	2 years ago
Andrew Waterman	de5094a1a9	Merge pull request #1812 from riscv-software-src/fix-1810 Further improve ISA-string input validation	2 years ago
Andrew Waterman	9a641bb03e	Validate Zvl ISA string correctly See #1810 for explanation of how this can go wrong. Resolves #1810	2 years ago
Andrew Waterman	19fdd76e05	Merge pull request #1811 from riscv-software-src/fix-1810 Validate Zvl ISA string correctly	2 years ago
Andrew Waterman	6b74bd669d	Validate Zvl ISA string correctly See #1810 for explanation of how this can go wrong. Resolves #1810	2 years ago
Andrew Waterman	52aff0233f	Merge pull request #1804 from ved-rivos/ssdbltrp_typo Fix error in reading right sstatus	2 years ago
Ved Shanbhogue	a8525b6243	fix error in reading right sstatus	2 years ago
Jerry Zhao	0cc5ecce05	Merge pull request #1807 from riscv-software-src/remove-compile-flags Remove --with-isa/priv compile flags	2 years ago
Jerry Zhao	c187be0a1e	Remove leftover config.h includes in dasm/log-parser	2 years ago
Jerry Zhao	b47080fea4	Remove --with-priv compile flag	2 years ago
Jerry Zhao	d90e6df9c3	Remove --with-isa compile-time option	2 years ago
Andrew Waterman	2e816f23cb	Merge pull request #1796 from cyyself/tmp_mcountinhibit add support for mcountinhibit CSR	2 years ago
YenHaoChen	d7ded0cf85	Merge pull request #1793 from rtwfroody/native_triggers2 Only implement one solution for native triggers.	2 years ago
Tim Newsome	0703b44b77	Only implement one solution for native triggers. When S-mode is present, use option 1 (disable triggers in M-mode unless MIE is set) from the Debug Spec. When S-mode is not present, use option 2 (implement mte and mpte bits in tcontrol). See discussion in #1777.	2 years ago
Tim Newsome	451a7dcdd7	triggers: Move allow_action() into common_match() They are always called together, and now we get the previous privilege behavior in both.	2 years ago
Tim Newsome	4abd669b3d	Make allow_action() take proc instead of state	2 years ago
Tim Newsome	9c5a20fbdb	Work if tcontrol doesn't exist.	2 years ago
Yangyu Chen	5a6b789855	add support for mcountinhibit CSR We hardwired mcountinihibit to 0 previously. Now, we implemented it. Signed-off-by: Yangyu Chen <cyy@cyyself.name>	2 years ago
Andrew Waterman	cb78f095de	Merge pull request #1797 from YenHaoChen/pr-vector vector: disassemble: Let operand ordering be vd, [vrf]s1, vs2 to vector multiply-add instructions	2 years ago
YenHaoChen	6a1a5db16b	vector: disassemble: Let operand ordering be vd, [vf]s1, vs2 to vector widening floating-point fused multiply-add instructions	2 years ago
YenHaoChen	b47d0baab3	vector: disassemble: Let operand ordering be vd, [vf]s1, vs2 to vector single-width floating-point fused multiply-add instructions	2 years ago
YenHaoChen	7f38a503d0	vector: disassemble: Let operand ordering be vd, [vr]s1, vs2 to vector widening integer multiply-add instructions	2 years ago
YenHaoChen	ff62109211	vector: disassemble: Let operand ordering be vd, [vr]s1, vs2 to vector single-width integer multiply-add instructions	2 years ago
Andrew Waterman	2538c1fb20	Merge pull request #1788 from riscv-software-src/support-larger-addresses Lift restriction on physical-address size	2 years ago
Andrew Waterman	3c5b1bb09e	Merge pull request #1779 from rtwfroody/trigger_timing For mcontrol6, default to BEFORE timing.	2 years ago
Andrew Waterman	3f556d66e2	Merge pull request #1791 from YenHaoChen/pr-pm pointer masking: Always apply sstatus.MXR regardless of effective V	2 years ago
YenHaoChen	84a212e93b	pointer masking: Always apply sstatus.MXR regardless of effective V ISA spec says "Setting MXR at HS-level overrides both VS-stage and G-stage execute-only permissions."	2 years ago
Andrew Waterman	272c149f37	Merge pull request #1789 from YenHaoChen/pr-pm pointer masking: Consider effective v bit instead of current v bit	2 years ago
YenHaoChen	61d277c49c	pointer masking: Consider effective v bit instead of current v bit A previous commit removes the effectiveness of MPRV to MXR. (https://github.com/riscv-software-src/riscv-isa-sim/pull/1784) However, the removal implies the MPRV affects point masking individually, and the MXR should consider the effective v bit.	2 years ago
Jerry Zhao	5029aa7ce8	Merge pull request #1787 from riscv-software-src/fix-cfg-priv	2 years ago
Andrew Waterman	52f045d9ba	Lift restriction on physical-address size It remains true that PTEs can only represent addresses >= 2^56, but there's no need to impose that constraint on untranslated accesses.	2 years ago
Andrew Waterman	16870946ed	Use create_mem_region for legacy -m argument	2 years ago
Andrew Waterman	eb85c33899	Check size_t bounds overflow in create_mem_region	2 years ago
Andrew Waterman	1b33b5426b	Factor out create_mem_region from parse_mem_layout	2 years ago
Andrew Waterman	60f02dd1d8	Merge pull request #1786 from YenHaoChen/pr-mcontrol triggers: Let mcontrol.match be default (0/equal) if maskmax is 0	2 years ago
Jerry Zhao	eb07f100a3	Use cmdline --priv flag when parsing proc configurations from DTB	2 years ago
YenHaoChen	1510a6e461	triggers: Let mcontrol.match be default (0/equal) if maskmax is 0	2 years ago
YenHaoChen	d13dc0b3e3	triggers: mcontrol: refactor: Add mcontrol_t::maskmax	2 years ago
Andrew Waterman	20cd44ade6	Merge pull request #1784 from YenHaoChen/pr-pm pointer masking: Pointer masking does not apply when MXR=1 regardless of MPRV in v1.0.0-rc2	2 years ago

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3507 Commits (18f4d0ff13ce8d6933ddaf080dfbc5aa2217d2ab) All Branches Search

3507 Commits (18f4d0ff13ce8d6933ddaf080dfbc5aa2217d2ab)

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