When compiled as PIE, executable can be loaded at any memory address.
Lately, OpenSBI switched to such behavior and spike was not able to load
it anymore. This patch add an additional load_offset parameter for
load_elf(). This load_offset value is passed as DRAM_BASE and used only
for ET_DYN elfs.
Signed-off-by: Clément Léger <cleger@rivosinc.com>
The spec says: "If vl=0, no operation is performed and the destination
register is not updated." in Section 14. Vector Reduction Operations.
The commit proposes setting the variable is_write to false when vl = 0,
which means not logging the write.
Based on Spec chapter 3.5
"An MRET or SRET instruction is used to return from a trap in M-mode or
S-mode, respectively. When executing an xRET instruction, if xPP holds
the value y, then ELP is set to the value of xPELP if yLPE is 1;
otherwise, it is set to NO_LP_EXPECTED; xPELP is set to NO_LP_EXPECTED."
The change follow the last statement after semicolon
"xPELP is set to NO_LP_EXPECTED"
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
As proposed in #1652, we made the following changes to MMIO device (factory)
plugin API, to mitigate current limitations and facilitate factory reuse.
- removed `sargs` from `device_factory_t`, and introduced a new type alias
`device_factory_sargs_t` to capture `<device_factory_t *, sargs>` pairs,
this is used to instantiate sim_t instances;
- changed the signature of `device_factory_t::generate_fdt` and
`device_factory_t::parse_from_fdt` to take on an extra `sargs` argument,
for instantiating devices with per-device arguments;
- made `device_factory_t` const and potentially resuable across multiple
`sim_t` instances.
The specification states that writes to read-only bits in a RW CSR are
ignored. The hstateen*[n] bits are read-only when mstateen*[n]=0. This
PR proposes ignoring writes to read-only hstateen*[n] bits when
mstateen*[n]=0 instead of writing the bits to 0.
1. Add EXT_ZICFISS for enable Zicfiss with zicfiss extension name.
2. Add new software exception with tval 3 for shadow stack.
3. Implement sspush_x1/sspush_x5/sspopchk_x1/sspopchk_x5/ssrdp/ssamoswap_w/ssamoswap_d.
4. Implement c_sspush_x1/c_sspopchk_x5 in c_lui.h which has same encoding.
5. Add new special access type ss_access in xlate_flags_t for checking special read/write permission in SS(Shadow Stack) page.
6. Add new ss_load/ss_store/ssamoswap to enable ss_access flag.
7. Check special pte(xwr=010) of SS page.
The henvcfg fields, i.e., PBMTE, STCE, and ADUE, are read-only 0 when
the corresponding bits in menvcfg are 0. Besides the reading behavior,
the spec also specified the writing behavior, i.e., ignoring writes.
This commit ignores writes to the henvcfg fields when read-only 0.
Reference: https://github.com/riscv/riscv-isa-manual/issues/1312
Andrew Waterman
Jerry Zhao
Clément Léger
rbuchner
YenHaoChen
Chih-Min Chao
Ved Shanbhogue
LIU Yu
xinyuwang-sifive
SuHsien Ho
Ming-Yi Lai