Dataflow through the PC is an ILP bottleneck. Reduce the critical code path
by memoizing the likely next PC.
The first time an instruction is cached, the assumption is that the likely
next PC is on the sequential path. Whenever the instruction is executed and
the next PC was mispredicted, correct it. This does the right thing for
jumps and heavily biased branches. The misprediction penalty is low enough
that doing something smarter for less-biased branches is unprofitable.
If main memory contained an LPAD instruction but the incoherent I$ contained
an unrelated instruction, then the landing-pad MSBs would not have been
checked. Fix by making the I$ coherent with the LPAD when the initial
landing-pad check is performed.
Add --dm-no-abstractauto flag to disable support for the optional abstractauto
register. When disabled, writes to the register are ignored and the internal state
is kept at 0.
Currently, neither riscv-openocd nor openocd support batch reads or writes for debug modules
that don’t implement abstractauto, as both assume every debug module provides
abstractauto support. However, work is underway to remove this dependency.
Same as the previous commit, but for Zicfiss. Can't
find the exact details in Unprivileged spec version 20251030,
but that must be a spec oversight. QEMU implements it the same
way e.g.
It's (normally) only reasonable to launch Spike as a background process
when it's used in a mode that does not need stdin. But we should
support those use cases without hanging. Fix the hang by catching
SIGTTOU.
For obvious reasons, `spike -d` will still hang waiting for input
until it's in the foreground.
Fixes#2133
This is already done for the disassembler (disasm/disasm.cc:882),
but the actual implementations haven't been updated.
A already implies Zaamo,Zalrsc and the other way around (both enabled imply A).
Makes the implementation slightly more correct for when only one standard
extensions is enabled out of the two.
See RISC-V Debug Specification Version 1.0 [6.1.5. Debug Module
Interface Access (`dmi`, at 0x11)], `op` field description:
> 0 (nop): Ignore data and address.
Don’t send anything over the DMI during Update-DR. This operation should
never affect DMI busy or error status.
The algorithm is as follows:
- An instruction-side Bloom filter knows which PPNs might be in the I$
- A store-side Bloom filter knows which PPNs might get store TLB hits
- When refilling the store TLB, search the I-Bloom filter; on a hit,
remove the ITLB entry, rebuild the I-Bloom filter, and flush the I$
- When refilling the ITLB, search the store-Bloom filter; on a hit,
remove the store TLB entry and rebuild the store-Bloom filter
The effect is that any word that can be stored-to cannot be in any I$.
The old scheme (periodically flush I$) was hacky and didn't correctly
respect the in-order fetch rule (i.e. fetches are in-order wrt.
each other, and so they see ordered stores in order).
Section 18.3 says
"The V extension supports all vector load and store instructions
(Section Vector Loads and Stores), except the V extension does not
support EEW=64 for index values when XLEN=32"
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Andrew Waterman
Zhibo Hong
Nadime Barhoumi
Ved Shanbhogue
mslijepc
Alexander Romanov
pierav
Sergei Zimmerman
Evgeniy Naydanov
Andrew Young
Chih-Min Chao
LIU Yu
Binno Shen