cce834e437
Support Ziccid extension
11 months ago
b6a061b683
Support Ziccif extension
11 months ago
d4abc9a71b
AIA: Enable Smcsrind/Sscsrind if supporting Smaia/Ssaia
Smaia/Ssaia allocates indirect CSRs 0x30~0x3f for major interrupt
priorities and 0x70~0xff for external interrupts (only with an IMSIC).
2 years ago
8050278445
AIA: Add isa=..._smaia_ssaia_... option
2 years ago
4764d3c029
Implement Ssccfg & Smcdeleg for spike
Signed-off-by: muhammad.moiz.hussain@semidynamics.com
1 year ago
4d3920b262
Add Svade extension Support
Spike always supports the Svade extension, this is required by the RVA and RVB profiles
1 year ago
b645cc0fba
Explicitly annotate fallthrough cases (-Wextra)
1 year ago
8ccde08b27
Remove unused functions (-Werror)
1 year ago
cfa593d0ea
isa_parser: don't append one char at a time in strtolower
This avoids potential re-alloations as it allocates the result string
upfront.
1 year ago
5ed426bbf4
Add Zvqdotq extension
Not yet frozen, but in a pretty stable state.
See https://github.com/riscv/riscv-dot-product
1 year ago
1e589aa502
Support strict disassembly in disassembler_t
1 year ago
ff771919ec
Updated load/store pair for RV32 to v0.10
- renamed Zcmlsd to Zclsd
- bumped version number
2 years ago
9a641bb03e
Validate Zvl ISA string correctly
See #1810 for explanation of how this can go wrong.
Resolves #1810
2 years ago
6b74bd669d
Validate Zvl ISA string correctly
See #1810 for explanation of how this can go wrong.
Resolves #1810
2 years ago
b47080fea4
Remove --with-priv compile flag
2 years ago
6a1a5db16b
vector: disassemble: Let operand ordering be vd, [vf]s1, vs2 to vector widening floating-point fused multiply-add instructions
2 years ago
b47d0baab3
vector: disassemble: Let operand ordering be vd, [vf]s1, vs2 to vector single-width floating-point fused multiply-add instructions
2 years ago
7f38a503d0
vector: disassemble: Let operand ordering be vd, [vr]s1, vs2 to vector widening integer multiply-add instructions
2 years ago
ff62109211
vector: disassemble: Let operand ordering be vd, [vr]s1, vs2 to vector single-width integer multiply-add instructions
2 years ago
9031c7b651
Fix ordering of B single-letter extension
The canonical order is IMAFDQLCBKJTPVH
Signed-off-by: Jerry Zhao <jerryz123@berkeley.edu>
2 years ago
c302e8bd16
Add Smdbltrp
2 years ago
0797c21001
Add Ssdbltrp
2 years ago
370f741a97
pointer masking: Support _ssnpm to --isa
2 years ago
eea20ae6a2
pointer masking: Support _smnpm to --isa
2 years ago
436b684ff5
pointer masking: Support _smmpm to --isa
2 years ago
6854a911fd
Expand default disassembly ISA
2 years ago
389851ce15
Add disassembly for Zfa extension
2 years ago
ef7416ce1d
Fix: Add missing <stdexcept> header for std::logic_error
- Included <stdexcept> in isa_parser.cc to resolve compilation error due to missing type 'std::logic_error'.
Signed-off-by: Rafael Sene <rafael@riscv.org>
2 years ago
67e205c289
Restrict spike to vlen <= 4096
2 years ago
457ea8c0cd
Relax zvfh/zvfhmin dependency on V, they only actually depend on Zve
2 years ago
9925435513
Allow disassembly from implementations that are not full V
2 years ago
ede537120b
Add Zvl/Zve validation to isa_parser
2 years ago
0408e797b1
Add isa_parser parsing for zvl/zve
2 years ago
c6cb05ceb7
In isa_parser, move extensionology code before error-checking code
Resolves #1696
2 years ago
70d26d64e6
Adding Zilsd and Zcmlsd extensions (Load/store pair for RV32)
2 years ago
c5229c3f5f
Add Zawrs extension
2 years ago
c4edeabbe7
Remove P, Zbpbo, Zpn, and Zpsfoperand from ISA parser
2 years ago
3a4f1702ed
Remove Zbpbo, Zpn, and Zpsfoperand from disassembler
2 years ago
55ee3a5916
Make Zba + Zbb + Zbs imply B in misa
2 years ago
b06c1e7bca
Make Zaamo + Zalrsc imply A in misa
2 years ago
624dd40817
Implement misa.B bit through --isa=...B...
2 years ago
9ba5bd3171
Add Zicfiss extension from CFI extension, v0.4.0
1. Add EXT_ZICFISS for enable Zicfiss with zicfiss extension name.
2. Add new software exception with tval 3 for shadow stack.
3. Implement sspush_x1/sspush_x5/sspopchk_x1/sspopchk_x5/ssrdp/ssamoswap_w/ssamoswap_d.
4. Implement c_sspush_x1/c_sspopchk_x5 in c_lui.h which has same encoding.
5. Add new special access type ss_access in xlate_flags_t for checking special read/write permission in SS(Shadow Stack) page.
6. Add new ss_load/ss_store/ssamoswap to enable ss_access flag.
7. Check special pte(xwr=010) of SS page.
3 years ago
5ca914b13c
Zicfilp: Support lpad instruction in disassembler
2 years ago
8e56ced020
Zicfilp: Add Zicfilp extension flag
2 years ago
0bf0a60ad8
Add Zaamo and Zalrsc extensions
2 years ago
075af7fd61
B=Zba+Zbb+Zbs
2 years ago
40baa0143e
Fix order of H extension in ISA string
According to Subset Naming Convention section of ISA Manual Volume I,
H extension should be after V extension in ISA string.
Signed-off-by: demin.han <demin.han@starfivetech.com>
2 years ago
da2f415bb6
Add srmcfg CSR
2 years ago
84f1dbaf8e
Add Zimop extension
2 years ago
6b2ea346b5
Fix formatting
2 years ago
Andrew Waterman
YenHaoChen
Muhammad Moiz Hussain
Mingzhu Yan
Mahmoud Abumandour
Christian Herber
Jerry Zhao
Ved Shanbhogue
Rafael Sene
SuHsien Ho
Ming-Yi Lai
demin.han