Tree: 0a59b06f3b

arrv-sc-arrv-sc/snippy-tests

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hwachav4

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itrigger-etrigger-cleanup

load_reservation_set_size

log-commits-faster

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p-ext-0.5.2

plctlab-plct-zce-fix2

plic-clint-endian

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priv-1.10

private-l1-caches

pte-info-and-delegation

remove-tests

rivosinc-etrigger_fix_exception_match

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speed2

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Commit Graph

2616 Commits (0a59b06f3b5542fab8d78ae3ee0b8276ec5acd36)

 

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Author	SHA1	Message	Date
Jerry Zhao	0a59b06f3b	Merge pull request #1209 from riscv-software-src/debugfix Fix debug-mode regression introduced by 20e7f53	3 years ago
Scott Johnson	b3946f8500	Merge pull request #1207 from YenHaoChen/pr-trap-trigger-common triggers: refactor: add trap_common_t	3 years ago
Jerry Zhao	7334b0180e	Fix debug-mode regression introduced by 20e7f53 - Debug mode should break the processor out of wfi - wfi in debug mode should execute as a nop	3 years ago
Andrew Waterman	4ac904b7c0	Merge pull request #1206 from riscv-software-src/always_misaligned Control whether misaligned accesses are supported via command line	3 years ago
YenHaoChen	89a44eb0a2	triggers: refactor: move mode_match() and textra_match() to private for protected	3 years ago
YenHaoChen	590a36e487	triggers: refactor: create trigger_t::common_match()	3 years ago
YenHaoChen	3b36645442	triggers: refactor: move textra_match() to protected from public	3 years ago
YenHaoChen	247f01691b	triggers: refactor: move textra_match() into detect_trap_match::detect_trap_match()	3 years ago
YenHaoChen	0a45912d60	triggers: refactor: move textra_match() into mcontrol_common_t::detect_memory_access_match()	3 years ago
YenHaoChen	6fd0169b32	triggers: refactor: move detect_trap_match() to trap_common_t from itrigger_t/etrigger_t	3 years ago
YenHaoChen	4cf0ef9c4e	triggers: refactor: create virtual function trap_common_t::simple_match()	3 years ago
YenHaoChen	c0cc59d5c4	triggers: refactor: move get_action() to trap_common_t from itrigger_t/etrigger_t	3 years ago
YenHaoChen	c8ea412319	triggers: refactor: move get_dmode() to trap_common_t from itrigger_t/etrigger_t	3 years ago
YenHaoChen	1517591add	triggers: refactor: move action variable to trap_common_t from itrigger_t/etrigger_t	3 years ago
YenHaoChen	5fa820d323	triggers: refactor: move hit variable to trap_common_t from itrigger_t/etrigger_t	3 years ago
YenHaoChen	1ffeac39c5	triggers: refactor: move dmode variable to trap_common_t from itrigger_t/etrigger_t	3 years ago
YenHaoChen	d9bc868d2c	triggers: refactor: add empty parent trap_common_t class for itrigger_t and etrigger_t	3 years ago
Andrew Waterman	1aac9da38f	Delete --enable-misaligned configure option	3 years ago
Andrew Waterman	b3dfcf1523	Respect --[no-]misaligned command-line flag	3 years ago
Andrew Waterman	a11af65d0e	Add --[no-]misaligned command-line options They don't do anything yet.	3 years ago
Andrew Waterman	8d084dbd09	Pass cfg object to processor_t constructor This reduces boilerplate as we add additional options.	3 years ago
Andrew Waterman	2a95b4e198	Merge pull request #1203 from riscv-software-src/misa-c-read-only Make misa.C read-only	3 years ago
Andrew Waterman	07647a9b53	Merge pull request #1200 from riscv-software-src/mmio_pte Support accessing PTEs through mmio_load/mmio_store	3 years ago
YenHaoChen	9f4a93dbf9	triggers: refactor: add bool etrigger_t::simple_match()	3 years ago
YenHaoChen	007199efdc	triggers: refactor: add bool itrigger_t::simple_match()	3 years ago
Andrew Waterman	96be756b53	Make misa.C read-only This resolves the issue discussed in #1201. Prior to 0adf9307, clearing misa.C would disable compressed instructions and increase IALIGN to 32. Afterwards, clearing misa.C had essentially no effect because Zca and friends would stay enabled. While AFAICS this isn't technically incorrect, it certainly doesn't follow the principle of least surprise. Instead, remove the feature to toggle misa.C. The effect is that misa.C is 1 iff C is included in the ISA string, and IALIGN is independent of misa.C: specifically, IALIGN is 16 iff Zca is present. (And of course C implies Zca.) Removing the alignment check on misa writes is not a separate commit because these two changes should be made atomically. Not checking the alignment on misa writes goes hand-in-hand with misa.C being read-only.	3 years ago
Andrew Waterman	85f7869bf5	Merge pull request #1205 from riscv-software-src/reservable Add method to probe which memory regions are reservable	3 years ago
Jerry Zhao	43474ddc63	Support pte load/store from mmio regions	3 years ago
Jerry Zhao	25f9028475	Pull pte load/store into methods of mmu_t	3 years ago
Jerry Zhao	c91fe0b0a6	Add method to probe which memory regions are reservable Default reservable regions is the same as before	3 years ago
Jerry Zhao	0d13d07a04	Remove extraneous semicolon from simif.h	3 years ago
Jerry Zhao	76ee37a1af	Specify addresses are physical for simif_t member functions	3 years ago
Scott Johnson	ad5fcd96e9	Merge pull request #1177 from YenHaoChen/pr-mcontrol6 Support mcontrol6 trigger	3 years ago
Andrew Waterman	e4126acfa4	Make obvious that PC alignment mask is a function of IALIGN No functional change.	3 years ago
Andrew Waterman	f11c7b64b4	Merge pull request #1197 from riscv-software-src/wfi Prevent processor_t from retiring instructions after a WFI	3 years ago
Jerry Zhao	20e7f5363b	Prevent processor_t from retiring instructions after a WFI	3 years ago
Andrew Waterman	591e622923	Merge pull request #1196 from riscv-software-src/readme_address Change address used in gdb debug example.	3 years ago
Tim Newsome	b282cafd59	Change address used in gdb debug example. PR #889 put a UART at 0x10000000, which conflicts with the old address. Fixes #1179.	3 years ago
Andrew Waterman	c94cafa66a	Merge pull request #1195 from riscv-software-src/mmio_type Expose access type in simif_t mmio_load interface	3 years ago
Andrew Waterman	205d8db0a8	Merge pull request #1194 from riscv-software-src/clean-up-makefiles Remove dead code in Makefiles	3 years ago
Jerry Zhao	15635c2553	Add mmio_fetch to simif_t to distinguish between fetch/load for mmio accesses	3 years ago
Andrew Waterman	dfc9b5fce1	Remove dead code in Makefile.in	3 years ago
Andrew Waterman	540c3ce056	Remove non-installed header lists from Makefile fragments It's just dead code. (Dependences on headers are auto-generated as `.d` files.)	3 years ago
Andrew Waterman	3349dc5113	Merge pull request #1192 from riscv-software-src/improve-histogram Slightly improve histogram feature	3 years ago
Andrew Waterman	662a00c595	Merge pull request #1191 from riscv-software-src/always_histogram Support histogram feature without configure option	3 years ago
Andrew Waterman	4ecbaf15df	Merge pull request #1147 from riscv-software-src/extension-namespace Support more than 65 Z* extensions	3 years ago
Andrew Waterman	8ed1919047	Merge pull request #1193 from riscv-software-src/fix-build-nondeterminism Fix build nondeterminism by deleting archives before recreating	3 years ago
Andrew Waterman	af399342a4	Fix build nondeterminism by deleting archives before recreating Otherwise, `ar rcs` will add to the previous archive, creating the possibility of multiple functions with the same name in the archive. The linker might not choose the most recent version, resulting in undefined behavior.	3 years ago
Andrew Waterman	d6e5a0ed89	Speed up histogramming by changing data structure Since we no longer rely on the map's order, use unordered_map.	3 years ago
Andrew Waterman	ea70167d28	Sort histogram printout count, rather than address	3 years ago