1. Add EXT_ZICFISS for enable Zicfiss with zicfiss extension name.
2. Add new software exception with tval 3 for shadow stack.
3. Implement sspush_x1/sspush_x5/sspopchk_x1/sspopchk_x5/ssrdp/ssamoswap_w/ssamoswap_d.
4. Implement c_sspush_x1/c_sspopchk_x5 in c_lui.h which has same encoding.
5. Add new special access type ss_access in xlate_flags_t for checking special read/write permission in SS(Shadow Stack) page.
6. Add new ss_load/ss_store/ssamoswap to enable ss_access flag.
7. Check special pte(xwr=010) of SS page.
According to Subset Naming Convention section of ISA Manual Volume I,
H extension should be after V extension in ISA string.
Signed-off-by: demin.han <demin.han@starfivetech.com>
Currently there is a bug with the disassembly when vsetivli/vsetvli have invalid vtypes (with reserved bits set). Spike correctly detects this and sets vill, but the disassembler integrated into spike ignores those bits being set and prints the instruction as if they weren't. This makes debugging harder, it looks like an otherwise valid vtype was being rejected and can lead down debugging paths like thinking the vector unit is configured incorrectly.
This commit changes the behaviour so that if these reserved bits are set, it prints out the hex value of the vtype. This is understood by the assembler.
GCC disassembler prints out the decimal value of the vtype in this case, I think that hex value is clearer but I can change it if desired.
Signed-off-by: Brendan Sweeney <brs@eecs.berkeley.edu>
In general, the strategy has been that the disassembler enables a
maximal set of non-conflicting extensions, thereby doing the right thing
for the largest number of users.
Add disassembler support for all instructions in Zvk extensions:
- Zvbb (bitmanip)
- Zvbc (carryless multiplication)
- Zvkg (GMAC)
- Zvkned (AES)
- Zvknha / Zvknhb (SHA-256, SHA-512)
- Zvksed (SM4)
- Zvksh (SM3)
Macros are used to limit code duplication, following the example
of the base V extension. Because the V extension undefines some
of its macros after their use, there Zvk support does define some
similar macros.
Co-authored-by: Gianluca Guida <gianluca@rivosinc.com>
Signed-off-by: Eric Gouriou <ego@rivosinc.com>
None of these cases are perf-critical.
It was easy to change one of them to use std::string, but the others
would have required more refactoring. So, simply change them to use
snprintf instead.
The shift amount is 6 bits wide on RV64. As with the base ISA shifts, we
ignore XLEN and unconditionally disassemble the 6-bit immediate on RV32.
Partially reverts da93bdc435
Iterate over the instruction chains in reverse order, prioritizing
the last call to `disassembler_t::add_insn`.
To preserve behavior for the standard instructions, reverse the order
in which we add instructions in the `disassembler_t` constructor.
Supersedes #995.
Before this patch, spike just had an "Xbitmanip" extension which
covered everything in the proposed bitmanip extension that hadn't been
ratified. The problem is that if you want to model (or verify) a
processor that targetted just some of the proposed bitmanip extension,
you couldn't configure Spike to do that.
For example, the lowRISC Ibex processor has several different
configurations. The "balanced" configuration targetted Zba, Zbb, Zbs,
Zbf and Zbt of the 0.92 spec. With the Zba, Zbb and Zbs ratified,
we'll now be able to use an ISA string like
rv32imc_Zba_Zbb_Zbs_XZbf_XZbt
and Spike will correctly fail to decode instructions like 'bcompress',
which would have been decoded with Xbitmanip.
This patch adds a new custom extension name for each part of the
extension that wasn't fully ratified. These have an 'X' prefix so, for
example, the bit permutation instructions that were proposed as Zbp
can be found under XZbp.
Specifying "Xbitmanip" gets all of these extensions, so its behaviour
should be unchanged.
Note that the slo(i) / sro(i) instructions have been moved from the
proposed Zbb to XZbp. This matches a comment in the Change History
section of v0.93 of the bitmanip spec: it seems that the authors
forgot to also move them in Table 2.1 (which gives the lists of
instructions for each extension). This change won't break anything
that currently exists, but it took quite a while to figure out what
was going on so I thought I'd leave a breadcrumb trail for the next
engineer!
The bulk of the patch is just defining some more entries in the
isa_extension_t enum and rewriting each of the instructions to depend
on the relevant entry. This is mostly a straight textual replacement
but it's slightly more complicated for things like the "pack"
instruction that are defined by several different proposed extensions.
It's helpful to attempt to disassemble instructions for disabled
extensions, so attempt to do so. Since some extensions conflict
in the opcode space, continue to give higher priorty to explicitly
enabled extensions.
Andrew Waterman
Jerry Zhao
Christian Herber
Ved Shanbhogue
SuHsien Ho
Ming-Yi Lai
demin.han
YenHaoChen
brs
Chih-Min Chao
Brendan Sweeney
Eric Gouriou
Philipp Tomsich
Gianluca Guida
Weiwei Li
Neel Gala
Kip Walker
liweiwei90
Yan
Rupert Swarbrick