1 Commits (0a048a93ebdab87473fcb50bc647e84098693cd0)

Author SHA1 Message Date
Quan Nguyen 9dbe0fac5f Move half precision instructions, add vfmsv, vfmvv 12 years ago
Albert Ou 826fc1719a Implement "half-baked" half-precision instruction subset for Hwacha 13 years ago
Andrew Waterman c8a8c07ec2 Use WRITE_RD/WRITE_FRD macros to write registers 13 years ago
Andrew Waterman 77452a26e7 temporary undoing of renaming 15 years ago
Andrew Waterman 740f981cfd [sim] renamed to riscv-isa-run 15 years ago
Andrew Waterman 2c3ff5536d [xcc,opcodes,pk,sim] krste's re-renaming spree 15 years ago
Andrew Waterman f0063c2e8b [sim, pk, xcc, opcodes] great instruction renaming of 2011 16 years ago
Andrew Waterman 7471eee0ba [xcc, sim, pk, opcodes] new instruction encoding! 16 years ago
Andrew Waterman cbefaf68c7 [xcc, sim] changed instruction format so imm12 subs for rs2 16 years ago
Andrew Waterman 2d75bf71bb [xcc,sim] implement FP using softfloat 16 years ago
Andrew Waterman c12327f15c [sim,xcc] Added first few Hauser FP insns (sign-injection) 16 years ago