Quan Nguyen
|
9dbe0fac5f
|
Move half precision instructions, add vfmsv, vfmvv
|
12 years ago |
Albert Ou
|
826fc1719a
|
Implement "half-baked" half-precision instruction subset for Hwacha
|
13 years ago |
Andrew Waterman
|
c8a8c07ec2
|
Use WRITE_RD/WRITE_FRD macros to write registers
|
13 years ago |
|
Andrew Waterman
|
bda232b011
|
Rename MFTX/MXTF to FMV
|
13 years ago |
Andrew Waterman
|
77452a26e7
|
temporary undoing of renaming
|
15 years ago |
|
Andrew Waterman
|
740f981cfd
|
[sim] renamed to riscv-isa-run
|
15 years ago |
Andrew Waterman
|
2c3ff5536d
|
[xcc,opcodes,pk,sim] krste's re-renaming spree
|
15 years ago |
|
Andrew Waterman
|
7471eee0ba
|
[xcc, sim, pk, opcodes] new instruction encoding!
|
16 years ago |
|
Andrew Waterman
|
cbefaf68c7
|
[xcc, sim] changed instruction format so imm12 subs for rs2
|
16 years ago |
|
Andrew Waterman
|
9bd1c58531
|
[sim, xcc] Added mffh.d/mtflh.d; fixed FP ABI for 32-bit
|
16 years ago |
|
Andrew Waterman
|
46697c22d4
|
[sim, xcc] bthread threading model exposed; insn encoding cleaned up
|
16 years ago |
|
Andrew Waterman
|
2d75bf71bb
|
[xcc,sim] implement FP using softfloat
The intersection of the Hauser FP and MIPS FP is implemented.
|
16 years ago |
|
Andrew Waterman
|
40998b4479
|
[xcc,pk,sim] Added first part of FP support
In particular, FP loads, stores, and moves now work.
|
16 years ago |
