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riscv-isa-sim
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1 Commits (0a048a93ebdab87473fcb50bc647e84098693cd0)

Author SHA1 Message Date
Quan Nguyen 9dbe0fac5f Move half precision instructions, add vfmsv, vfmvv
12 years ago
Andrew Waterman c8a8c07ec2 Use WRITE_RD/WRITE_FRD macros to write registers
13 years ago
Andrew Waterman e07148ac53 Implement zany immediates
13 years ago
Andrew Waterman 77452a26e7 temporary undoing of renaming
15 years ago
Andrew Waterman 740f981cfd [sim] renamed to riscv-isa-run
15 years ago
Andrew Waterman 7471eee0ba [xcc, sim, pk, opcodes] new instruction encoding!
16 years ago
Andrew Waterman cbefaf68c7 [xcc, sim] changed instruction format so imm12 subs for rs2
16 years ago
Andrew Waterman e8125348b3 [sim,xcc] Changed instruction format to RISC-V
16 years ago
Andrew Waterman 01c01cc36f Reorganized directory structure
16 years ago