riscv
/
riscv-isa-sim
mirror of https://github.com/riscv-software-src/riscv-isa-sim.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
343 Commits
53 Branches
3 Tags
19 MiB
Tree: 0a048a93eb
Branches Tags
${ item.name }
Create tag ${ searchTerm }
Create branch ${ searchTerm }
from '0a048a93eb'
${ noResults }
Commit Graph

8 Commits (0a048a93ebdab87473fcb50bc647e84098693cd0)

Author SHA1 Message Date
Quan Nguyen 9dbe0fac5f Move half precision instructions, add vfmsv, vfmvv
12 years ago
Andrew Waterman aedcd67ac8 Update to new privileged ISA
13 years ago
Albert Ou ad42696405 Fix declaration of half-precision instructions
13 years ago
Albert Ou c258e24c0a Re-add Hwacha header file
13 years ago
Albert Ou 826fc1719a Implement "half-baked" half-precision instruction subset for Hwacha
13 years ago
Yunsup Lee cb6cfc5f3a refactor disassembler, and add hwacha disassembler
13 years ago
Yunsup Lee 2f1f9a4fbc revamp hwacha; now runs in physical mode
13 years ago