This implements the Zicond (conditional integer operations) extension,
as of version 1.0-draft-20230120.
The Zicond extension acts as a building block for branchless sequences
including conditional-arithmetic, conditional-logic and
conditional-select/move.
The following instructions constitute Zicond:
- czero.eqz rd, rs1, rs2 => rd = (rs2 == 0) ? 0 : rs1
- czero.nez rd, rs1, rs2 => rd = (rs2 != 0) ? 0 : rs1
See
https://github.com/riscv/riscv-zicond/releases/download/v1.0-draft-20230120/riscv-zicond_1.0-draft-20230120.pdf
for the proposed specification and usage details.
The addition of Svadu support and removal of --mmu-dirty
command line flag results in the dirty_enabled configuration state
no longer being used. Remove the remnants of this state.
The Svadu (https://github.com/riscv/riscv-svadu) extension updates
the A/D bits of PTEs:
1. In S/HS mode when menvcfg.hade=1
2. In G-stage page tables when menvcfg.hade=1
3. In VS mode when henvcfg.hade=1
To enable this behavior the 'svadu' ISA string is needed.
This newly added behavior supplants the --mmu-dirty flag. However,
that flag is not yet removed.
Add in the support for the HADE fields in menvcfg and henvcfg
based off of the svadu ISA string. This only allows for the writable
HADE bits being exposed when the svadu ISA string is employed. No
other behavior is implemented.
Delete the old branch and pull a new one, because of a wrong force push. Git is not as easy as I think.
Signed-off-by: gr816ox <50945677+gr816ox@users.noreply.github.com>
This fixes a bug where --isa=rv64imafdc would fail to set
extension_table['F'] because of the ad hoc manner in which we were
synchronizing max_isa and extension_table.
As recommended in the debug spec table "Suggested Trigger Timings", to
avoid the footgun of replaying a load (which may have side effects) when
the breakpoint trap handler returns.
reference: https://github.com/riscv-software-src/riscv-isa-sim/pull/1208#issuecomment-1373035906
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The legalize_timing() depends on select, execution, load, and store,
which are updated in the same function tdata1_write(). As a result,
reordering statements in the tdata1_write() may break the functionality.
Passing those variables as parameters to legalize_timing() does not
solve the problem. Thus, we give the original write value and the masks
of the variables to the legalize_timing(). This makes the legalization
function independent of the updating variables and resolves the issue.
reference: https://github.com/riscv-software-src/riscv-isa-sim/pull/1214
Andrew Waterman
Neel Gala
Jerry Zhao
Philipp Tomsich
Scott Johnson
YenHaoChen
Aaron Durbin
gr816ox