riscv-isa-sim

Commit Graph

Author	SHA1	Message	Date
Philipp Tomsich	f002b931d0	encoding.h: regenerate	3 years ago
Philipp Tomsich	50a48e1517	gitignore: ignore emacs backup files	3 years ago
Andrew Waterman	d70ea67df7	Merge pull request #1262 from jolivain/fix_spike_usage_message Fix --bootargs default value in spike usage help() function	3 years ago
Julien Olivain	04dbf0d5be	Fix --bootargs default value in spike usage help() function Commit `191634d285` changed the default kernel boot args from "console=hvc0 earlycon=sbi" to "console=ttyS0 earlycon", but didn't updated the spike usage help() function. This commit introduces a new macro DEFAULT_KERNEL_BOOTARGS in order to have a single definition. This macro is used everywhere in dts.cc and spike.cc help() function. Signed-off-by: Julien Olivain <ju.o@free.fr>	3 years ago
Jerry Zhao	929ff56a09	Merge pull request #1297 from riscv-software-src/zicntr_zihpm Stop unconditionally adding zicntr/zihpm to supported extensions	3 years ago
Jerry Zhao	9641cf5b5a	Stop unconditionally adding zicntr_zihpm to extensions	3 years ago
Jerry Zhao	41934578a4	Support zihpm && !zicntr	3 years ago
Jerry Zhao	f9c78b8e05	Set counteren_mask properly when !(zihpm && zicntr)	3 years ago
Jerry Zhao	384316fb36	Add zicntr_zihpm to DEFAULT_ISA	3 years ago
Jerry Zhao	5e366af773	Update configure/config.h.in Ran autoreconf in top directory, version 2.69	3 years ago
Jerry Zhao	a6eb6c2a99	Merge pull request #1294 from riscv-software-src/wfi_accessor Add processor_t::is_waiting_for_interrupt accessor	3 years ago
Jerry Zhao	1545955298	Add processor_t::is_waiting_for_interrupt accessor Signed-off-by: Jerry Zhao <jerryz123@berkeley.edu>	3 years ago
Andrew Waterman	4b0e34e013	Merge pull request #1279 from riscv-software-src/jerryz123-patch-1 Improve ctrlc responsiveness in interactive mode	3 years ago
Jerry Zhao	99a98013a4	interactive: Improve ctrlc responsiveness * Move most ctrl-c logic to interactive() * `5f4cabc` was only a partial fix. This change catches more corner cases where the ctrlc is registered Signed-off-by: Jerry Zhao <jerryz123@berkeley.edu>	3 years ago
Andrew Waterman	8983efd146	Merge pull request #1292 from TommyMurphyTM1234/master Fix for #1291	3 years ago
Andrew Waterman	e3689fc92a	Merge pull request #1286 from riscv-software-src/smrnmi Implement Smrnmi extension	3 years ago
Tommy Murphy	93c6d8e1e0	Fix for https://github.com/riscv-software-src/riscv-isa-sim/issues/1291	3 years ago
Andrew Waterman	a5fdc4efbf	Implement Smrnmi extension We don't model any sources of RNMI, so this is mostly vestigial.	3 years ago
Andrew Waterman	43c87e5ccc	Make MPRV logic consistent; factor it out I believe the fact that mmu_t::refill_tlb was ignoring debug mode was benign, but certainly paying attention to debug mode is OK.	3 years ago
Andrew Waterman	b947fcb059	Update encoding.h for Smrnmi CSR and opcode definitions	3 years ago
Andrew Waterman	f29dcd0d34	Merge pull request #1284 from jolivain/fix_gcc13_build fesvr: fix compilation with gcc 13	3 years ago
Andrew Waterman	a6ec93c6b6	Merge pull request #1285 from plctlab/plct-zc-update-v1.0.3 Fix the relationship between Zce and Zcf	3 years ago
Weiwei Li	00066cb365	Fix the relationship between Zce and Zcf	3 years ago
Julien Olivain	0a7bb5403d	fesvr: fix compilation with gcc 13 Compiling spike with gcc 13 (for example, included in Fedora 38 prerelease) fails with error: In file included from fesvr/syscall.h:6, from fesvr/syscall.cc:4: fesvr/device.h:15:30: error: ‘uint64_t’ was not declared in this scope 15 \| typedef std::function<void(uint64_t)> callback_t; \| ^~~~~~~~ This is due to a gcc header dependency change. See for reference: https://gcc.gnu.org/gcc-13/porting_to.html#header-dep-changes This commit explicitly adds the missing <cstdint> header inclusion to fix this build failure. Signed-off-by: Julien Olivain <ju.o@free.fr>	3 years ago
Andrew Waterman	a35865f0f5	Merge pull request #1276 from scottj97/clint-simif Use simif_t for devices	3 years ago
Scott Johnson	1d721b7940	Use simif_t instead of sim_t for clint/plic In keeping with the spirit of simif_t.	3 years ago
Scott Johnson	747c1a529e	Switch debug_module to use simif_t instead of sim_t In keeping with the spirit of simif_t.	3 years ago
Scott Johnson	d7632c8d7f	Move debug_mmu used by debug_module up to simif_t	3 years ago
Scott Johnson	1ffef82ac1	Move methods used by debug_module/clint/plic up to simif_t So we can soon convert those classes to use simif_t instead of sim_t.	3 years ago
Scott Johnson	f01094d03b	Add virtual/override to sim_t declarations To be explicit about which methods of simif_t and htif_t we implement.	3 years ago
Jerry Zhao	34bebfe311	Merge pull request #1274 from riscv-software-src/more-symbols Add +symbol_elf flag to fesvr to support loading in symbols from other elf files	3 years ago
Jerry Zhao	ca2b1000db	fesvr: Add --symbol-elf flag to populate htif-t::symbol_elfs	3 years ago
Jerry Zhao	76a4414381	fesvr: Add symbol_elfs field to htif_t When populated, symbol_elfs are additional elf files that populate the addr2symbol map in htif	3 years ago
Andrew Waterman	5f3dffe915	Merge pull request #1275 from riscv-software-src/jerryz123-patch-1 Fix ctrl-c responsiveness when running in interactive mode	3 years ago
Jerry Zhao	5f4cabc71e	Fix ctrl-c responsiveness when running-silent in interactive mode Break out of the interactive_run->interactive_run loop when ctrlc_pressed Signed-off-by: Jerry Zhao <jerryz123@berkeley.edu>	3 years ago
Jerry Zhao	9893d6e939	fesvr: Fix brace style in htif_t::load_program	3 years ago
Andrew Waterman	c97fb920b2	Merge pull request #1273 from riscv-software-src/fix-targargs Support passing in htif target-arguments through plusargs	3 years ago
Jerry Zhao	1851b45baf	fesvr: fix +signature-granularity opt parsing to be required_arg	3 years ago
Jerry Zhao	0243455b27	fesvr: Add +target-argument= flag to htif parsing	3 years ago
Jerry Zhao	422d297ef0	fesvr: Fix spacing in parse_arguments	3 years ago
Jerry Zhao	6c018d2e56	fesvr: target_args() should return a const	3 years ago
Jerry Zhao	cd0a5dc550	Merge pull request #1272 from sagark/targs-protected make target_args() protected instead of private to allow subclasses to inject args	3 years ago
Sagar Karandikar	34b018ab3a	make target_args() protected instead of private to allow subclasses to inject args	3 years ago
Andrew Waterman	6d6858ce7e	Merge pull request #1268 from riscv-software-src/more-plic-fixes Don't issue misaligned or non-power-of-2 MMIO accesses	3 years ago
Scott Johnson	1951f80361	Don't issue misaligned or non-power-of-2 MMIO accesses @aswaterman explains: Rather than requiring each MMIO device to support arbitrary sizes and alignments, decompose MMIO misaligned loads and stores in such a way as to guarantee their constituent parts are always aligned. (Specifically, they now always decompose to a sequence of one-byte accesses.) This is not a semantic change for main-memory accesses, but it is a semantic change for I/O devices. It makes them more realistic, in that most bus standards don't support non-power-of-2-sized accesses.	3 years ago
Scott Johnson	360e55535d	Fix misaligned accesses to clint's msip regs Misaligned MMIO is unspecified but this is simple enough.	3 years ago
Andrew Waterman	05f21fa250	Improve plic_context_t initialization style	3 years ago
Andrew Waterman	6ff727a3da	Merge pull request #1251 from plctlab/plct-zc-update-v1.0.3 update support for Zc* to v1.0.3	3 years ago
Andrew Waterman	8c5a857cec	Merge pull request #1267 from scottj97/clint-initialize-mtip Initialize MTIP at reset	3 years ago
Andrew Waterman	aa10facde0	Merge pull request #1266 from riscv-software-src/fix-o0-compile Define sim_t::INTERLEAVE so that it can be accessed by reference	3 years ago

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2895 Commits (08053dc9478dd43a4969697e55de62b8b4c4922f) All Branches Search

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