Branch: tweak_debug_rom

arrv-sc-arrv-sc/snippy-tests

confprec

cs250

cycleh

debug_rom

debug_rom_fence

device_flags

dtm_reset_error

dts_parsing

dynamic

eos18-bringup

factor-out-macros

fetch

fix-bf16

force-rtti

fp-encoding

heterogeneous_mc

hwachav4

increase-stack-size

itrigger-etrigger-cleanup

load_reservation_set_size

log-commits-faster

master

mmio-hack

mvp

no_progbuf

no_progbuf2

nolibfdt

p-ext-0.5.2

plctlab-plct-zce-fix2

plic-clint-endian

plic_uart_v1

priv-1.10

private-l1-caches

pte-info-and-delegation

remove-tests

rivosinc-etrigger_fix_exception_match

rva-profile-support

sanitize

simplify-misaligned

sodor

sparse-mem

speed2

speedup-hacks

static-link

test

tmp

trigger_priority

tweak_debug_rom

whole-archive

zvmm

dummy-tag-for-ci-storage

v1.0.0

v1.1.0

Branches Tags

${ item.name }

Create tag ${ searchTerm }

Create branch ${ searchTerm }

from 'tweak_debug_rom'

${ noResults }

Commit Graph

894 Commits (tweak_debug_rom)

 

All Branches   

Search

Author	SHA1	Message	Date
Megan Wachs	cc6a9c97e2	Debug ROM: Adjust debug ROM to have fewer icache flushes	8 years ago
Andrew Waterman	c0172e96bc	When no arguments are passed, print spike help, not fesvr help	8 years ago
Prashanth Mundkur	2dbcb01ca1	Allow querying the mmu configuration chosen during the build. (#191)	8 years ago
Andrew Waterman	4856220f05	Revert "Fix for issue #183: No illegal instruction exception for c.sxxi instructions encoded with zero shift amount" This reverts commit be0555d585. See #190	8 years ago
Palmer Dabbelt	3242d9b918	Merge pull request #189 from pmundkur/pm-csr-name-api Add an api to get the name for a CSR.	8 years ago
Prashanth Mundkur	fa2aaa3f8a	Add an api to get the name for a CSR.	8 years ago
Andrew Waterman	1da69b975b	Implement Hauser misa.C misalignment proposal (#187) See 0472bcdd16 - Reads of xEPC[1] are masked when RVC is disabled - Writes to MISA are suppressed if they would cause a misaligned fetch - Misaligned PCs no longer need to be checked upon fetch	8 years ago
Prashanth Mundkur	ec79312862	Fix the access exception during page-table walks to match the original access type, as specified in the manual. (#185)	8 years ago
Tim Newsome	0020b3b924	Fix spike-dasm. (#184) It had been broken by 90bafe660b.	8 years ago
Tim Newsome	b4997aa4be	Merge pull request #182 from riscv/reset_bits Implement debug havereset bits	8 years ago
Tim Newsome	90bafe660b	Implement debug havereset bits	8 years ago
Andrew Waterman	403438d609	Merge branch 'deepsrc-b_fix_issue183'	8 years ago
Shubhodeep Roy Choudhury	be0555d585	Fix for issue #183: No illegal instruction exception for c.sxxi instructions encoded with zero shift amount	8 years ago
Prashanth Mundkur	7e35a2a62f	Fix a bug caused by moving misa into state_t. (#180) * Fix misa losing its value in processor constructor due to state:reset() following state.misa initialization. Make state:reset() preserve misa. * Set state.misa to max_isa on reset(). * Idiomatic fix for earlier commit.	8 years ago
Prashanth Mundkur	bdd229b9ea	Move processor.isa to state.misa, since it really belongs there.	8 years ago
Tim Newsome	64947480de	Fix single stepping csrrw instructions (#178) This code is still a bit voodoo to me, but now we pass all the tests again. (Stepping was broken by 4299874ad4b07ef457776513a64e5b2397a6a75e.)	8 years ago
Tim Newsome	9d1e10a36e	Merge pull request #177 from riscv/debug_auth Add debug module authentication.	8 years ago
Prashanth Mundkur	4a97a05a6e	Narrow the interface used by the processors and memory to the top-level simulator/htif. This allows the implementation of an alternative top-level simulator class.	8 years ago
Prashanth Mundkur	58aa702359	Fix install of a missed header from debug_rom. The installed header files from the riscv subproject were incomplete, since processor.h includes debug_rom_defines.h, and the latter was not installed. Fix by moving it into riscv/, add it to the riscv subproject header list, which ensures it will get installed. While here, also add a missed dependency of debug_rom on riscv/encoding.h to debug_rom/Makefile.	8 years ago
Prashanth Mundkur	1fb7753da0	Fix a missed header file in the softfloat include install.	8 years ago
Andrew Waterman	4299874ad4	Implement clearing-misa.C-while-PC-is-misaligned proposal See https://github.com/riscv/riscv-isa-manual/pull/139 Not adopted yet, but I'm putting the implementation here for reference.	8 years ago
Andrew Waterman	e91d3a441e	Enforce 2-byte alignment of mepc/sepc/dpc	8 years ago
Tim Newsome	dfa7a56754	Merge pull request #173 from riscv/no_progbuf3 Add support for abstract debug access to CSRs and FPRs	8 years ago
Tim Newsome	aa8cbb1ccd	Add debug module authentication. Off by default, enabled with --debug-auth. The protocol is very simple (definitely not secure) to allow debuggers to test their authentication feature. To authenticate a debugger must: 1. Read authdata 2. Write to authdata the value that it just read, plus 1	8 years ago
Andrew Waterman	0329b0741a	Don't allow 32-bit instructions to take up multiple slots in I$ I$ indices now maintain a 1:N relationship with PCs. This is somewhat faster and also simpler.	8 years ago
Tim Newsome	c746388b54	Merge pull request #171 from riscv/sysbusbits Add support for debug bus mastering	8 years ago
Tim Newsome	3ef324120f	Passes smoke tests with --progsize=0	8 years ago
Tim Newsome	bb8c45f12e	WIP. Doesn't work.	8 years ago
Andrew Waterman	4c1c92f59f	Implement cycleh/instreth CSRs for RV32 (#172)	8 years ago
Tim Newsome	b2672e5d52	Add --debug-sba option This lets the user control whether the system bus access implements bus mastering.	8 years ago
Tim Newsome	d3d3681f34	Update debug_defines	8 years ago
Tim Newsome	cd1e73b4ed	Support debug system bus access.	8 years ago
Tim Newsome	11780eabc0	Use new debug_defines.h.	8 years ago
Jonathan Neuschäfer	fd0dbf46c3	mem_t: Throw an error if zero-sized memory is requested (#168) * mem_t: Throw an error if zero-sized memory is requested If for some reason the user requests a memory size of 0 megabytes, print a useful error message. * Check for overflow in memory size If the user passes in a large enough memory size (-m) that the size in bytes doesn't fit into size_t, catch this error in the make_mems function.	8 years ago
Andrew Waterman	874e55888f	Add some missing RVC instructions to disassembler	8 years ago
Tim Newsome	0185d36915	Merge pull request #165 from riscv/small_progbuf Add support for program buffer of size 2	8 years ago
Tim Newsome	e58dffd30d	Update debug_defines to latest version.	8 years ago
Tim Newsome	3582bab419	Set impebreak.	9 years ago
Tim Newsome	fa09d8179f	Update to latest debug_defines.h.	9 years ago
Tim Newsome	46a6786091	Make progbuf a run-time option. Also add an implicit ebreak after the program buffer. This is not part of the spec, but hopefully it will be.	9 years ago
Andrew Waterman	12714e371e	Rename badaddr to tval	8 years ago
Andrew Waterman	a06091861c	Rename sptbr to satp	8 years ago
Andrew Waterman	160c1a5cee	Set tval to 0 on traps with no specified tval Simply not writing the register was not a conformant implementation.	8 years ago
Andrew Waterman	d7ceeabbe6	Implement priv-1.11 interrupt-priority scheme (#161) Closes #159. a62e76cb16	8 years ago
Christopher Celio	86426a3336	Fix commitlog. (#162) A regression caused any instruction with rd=x0 to not be emitted.	8 years ago
Andrew Waterman	f8a83a8052	Merge pull request #156 from p12nGH/noncontiguous_harts Support for non-contiguous hartids	8 years ago
Gleb Gagarin	6c7c772b16	hartids knob description added	8 years ago
Gleb Gagarin	85efaaaba8	Support for non-contiguous hartids	8 years ago
Andrew Waterman	f5bdc2e342	Remove redundant U/S mode advertisement	9 years ago
Andrew Waterman	f87cdfec1d	H-mode no longer exists It's supplanted by the hypervisor extension, which doesn't use the privilege encoding of 2; it still looks like supervisor (i.e. 1).	9 years ago