Precompiled headers were broken because they weren't compiled with
the same -fPIC setting as the rest of the code. Fix by just making
everything use -fPIC.
- Remove remaining code which allowed spike to differentiate between
RV32 and RV64 instructions which share an encoding.
On branch scalar-crypto
Changes to be committed:
modified: disasm/disasm.cc
modified: riscv/processor.cc
- These are no longer needed since none of the scalar crypto instructions
overlap their encodings any more.
- There is more code to be removed in relation to letting Spike handle
overlapped RV32/64 instructions, but this will be done in subsequent commits
and PRs so that the downstream scalar-crypto work can be un-gated.
On branch scalar-crypto
Changes to be committed:
modified: riscv/encoding.h
On branch scalar-crypto
Changes to be committed:
modified: riscv/insns/sm3p0.h
modified: riscv/insns/sm3p1.h
modified: riscv/insns/sm4ed.h
modified: riscv/insns/sm4ks.h
- Words shouldn't be swapped based on enddianness; the lower-numbered
register always holds the low-order bits.
- Check for alignment, which also fixes a buffer overflow.
- Handle x0 correctly: read as zero, discard writes.
When V=1, vsstatus.MXR applies to the first stage of translation,
and mstatus.MXR applies to both.
mstatus.SUM doesn't apply when V=1, but vsstatus.SUM does.
The previous scheme flushed the TLB before and after HLV/HSV. I think
this was slightly wrong in the case of a debug trigger match: because
the TLB gets refilled before the trigger exception gets thrown, we might
not have reached the second TLB flush, so the entry could linger.
Instead of flushing, simply don't access the TLB and don't refill the
TLB for these instructions. Other than the trigger exception case,
the effect is the same: we'll perform a full table walk and we won't
cache the result.
* Priv virtual memory updates
* Priv 1.12 requires page faults when the address translation process
reaches a PTE with any reserved bit set
* Svpbmt uses two PTE bits, but otherwise has no effect on Spike (since
Spike is sequentially consistent and does not model PMAs)
* Add Svinval instructions
Even though I updated riscv-opcodes separately, I merged the new
defines into riscv/encoding.h manually, because riscv-opcodes seems
to be a step ahead of riscv-isa-sim for a few vector opcodes, causing
conflicts when regenerating encoding.h...
If that gets fixed, and encoding.h gets regenerated automatically, I can
remove it from this PR to avoid conflicts.
* Svinval: use #include rather than copying code
..for the Svinval functions that are implemented in ways that just
mimic SFENCE/HFENCE instructions
Thanks to @aswaterman for the suggestion
The wrong instruction might've been fetched when the PC was on the same
page as a load or store used within the MPRV sequence.
Fix by not using TLB within MPRV sequences.
Resolves#746
When U-mode is enabled but S-mode is disabled, `mcounteren` should control the availability of the hardware performance-monitoring counters in U-mode, and `scounteren` should be ignored.
The current implementation (incorrectly) raises an illegal instruction trap when reading performance-monitoring counters in U-mode while S-mode is disabled, even if the counters are enabled in `mcounteren`.
- Reverts the AES32 and SM4 instruction encodings back to a normal R-type
encoding, per the advice of the architecture reviewers.
On branch scalar-crypto-v0.9.2
Changes to be committed:
modified: riscv/encoding.h
modified: riscv/insns/aes32dsi.h
modified: riscv/insns/aes32dsmi.h
modified: riscv/insns/aes32esi.h
modified: riscv/insns/aes32esmi.h
modified: riscv/insns/sm4ed.h
modified: riscv/insns/sm4ks.h
problem:
when the following memory region is specified
-m0x00410000:0x1000,
0x00410200:0x1000,
0x00410400:0x1000,
0x00410600:0x1000,
0x00410800:0x1000,
0x00411000:0x1000,
0x00412000:0x1000,
0x00413000:0x1000,
0x00414000:0x1000
The error is
ERROR (duplicate_node_names): Duplicate node name /memory@410
ERROR (duplicate_node_names): Duplicate node name /memory@410
ERROR (duplicate_node_names): Duplicate node name /memory@410
ERROR (duplicate_node_names): Duplicate node name /memory@410
ERROR (duplicate_node_names): Duplicate node name /memory@410
ERROR (duplicate_node_names): Duplicate node name /memory@410
ERROR: Input tree has errors, aborting (use -f to force output)
cause:
the merge_overlapping_memory_regions works not well in partial overlap case
change:
1. use forward way to avoid weird reverse iterator behavior in C++
2. use address but not page number since the base addresses are
all aligned in make_mems
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
After the privilege draft-20191120-569d071, the section 3.1.6.3 says
"An MRET or SRET instruction that changes the privilege mode to
a mode less privileged than M also sets MPRV=0.
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Andrew Waterman
Ben Marshall
ChunPing Chung
Mark Fedorov
Chih-Min Chao
Dan Lustig
Lu_Reaper
sven
Shay Aviv
Jiuyang Liu