riscv-isa-sim

Commit Graph

Author	SHA1	Message	Date
kritik bhimani	90a04da3f9	fesvr: decrease DTM idle cycles	9 years ago
kritik bhimani	c39aaf7b23	fesvr: add support for system bus access	9 years ago
Albert Ou	f2ad9ace22	fesvr: Add --enable-sodor configure option	7 years ago
Udit Khanna	b95af7cdd2	Require VM enabled for SFENCE.VMA and S-mode for mstatus.SUM (#367 ) * SFENCE.VMA requires S-mode * MSTATUS.SUM hardwired to 0 if no S-Mode	7 years ago
Andrew Waterman	77661f72f8	Initialize mtime Closes #363	7 years ago
Andrew Waterman	1f34121c90	Fix (benign) uninitialized variable	7 years ago
Andrew Waterman	b36b0d66d9	Initialize state.misa prior to calls to supports_extension Partially reverts `0162a6e724` Closes #361	7 years ago
Andrew Waterman	c3b28ab3c6	add vaaddu/vasubu/vfncvt.rod.f.f.v to diassembler	7 years ago
Andrew Waterman	4679a2c981	Re-encode vaadd/vasub; remove vaadd.vi; add vaaddu/vasubu	7 years ago
Andrew Waterman	2704790df5	Merge pull request #356 from riscv/priv-flag Add --priv command-line option to set which privilege modes are available	7 years ago
Andrew Waterman	86857aa351	mstatus.FS only exists if (S \|\| V \|\| F)	7 years ago
Andrew Waterman	9a8ee5efdc	Remove S-mode interrupts when S-mode not present	7 years ago
Andrew Waterman	9b06f14085	Fix mode-transition logic when S-mode not present	7 years ago
Andrew Waterman	f29ea12a77	SRET requires S-mode	7 years ago
Andrew Waterman	4b7e763d24	Remove S-mode CSRs when S-mode is not present	7 years ago
Andrew Waterman	8ffefbc9a1	Add --priv option to control which privilege modes are available	7 years ago
Andrew Waterman	24e587d433	Factor out boilerplate strtolower function	7 years ago
Andrew Waterman	0162a6e724	In parse_isa_string, populate max_isa rather than state.misa reset will copy max_isa over to state.misa.	7 years ago
Andrew Waterman	ff81dea859	Merge pull request #355 from chihminchao/rvv-0.8-2019-11 rvv-0.8-2019-11	7 years ago
Chih-Min Chao	c8da0f2446	rvv: update version information Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	7 years ago
Chih-Min Chao	4ea09d92bd	rvv: add 'V' ext check for each vector insn 'require_vector' should appear in front of each instruction and this trigger illegal exception when V extension isn't supported. Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	7 years ago
Chih-Min Chao	32be2f9bc5	rvv: fix reg checking for vmadc/vmsbc remove unecessary checking Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	7 years ago
Chih-Min Chao	4808f84a18	rvv: add reg checking for specifial instructions Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	7 years ago
Chih-Min Chao	e289b996c6	rvv: add reg checking rule to vslide instructions Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	7 years ago
Chih-Min Chao	c655b1cf46	rvv: add reg checking rule for ldst include 1. unit-stride 2. strided 3. indexed 4. fault-first Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	7 years ago
Chih-Min Chao	f5a68933e5	rvv: add reg checking rule for general fomrat for most instruction which are in single, single, single/scalar/immediate format Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	7 years ago
Chih-Min Chao	b15c431738	rvv: add reg checking rule for comparison instrucitons include: 1. integer comparison 2. float comparison Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	7 years ago
Chih-Min Chao	5fc6d00602	rvv: add reg checking rule for reduction include 1. vredxxx 2. vwredxxx since reduction keep the accumulation result in pipeline and write 1 widen element back to dst register. Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	7 years ago
Chih-Min Chao	1cd989add9	rvv: add register using check for wide and narrow insn include 1. narrow shift 2. narrow clip 3. wide mac Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	7 years ago
Chih-Min Chao	60e3ed4952	rvv: refine vsetvl[i] logic 1. fix the ELAN check for vill 2. handle 'rs1 = x0' 3. make logic more readable Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	7 years ago
Chih-Min Chao	8f555c55a7	rvv: fix vsmul sign and variable type Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	7 years ago
Chih-Min Chao	3ccf946e6d	rvv: fix vssr/vssra rounding issue use 128bit to store temporary result to handle shift = 63 case in rv64 Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	7 years ago
Albert Ou	4cdecf219b	rvv: fix the rounding bit position for vnclip instructions. 1. The rounding increment should be derived from the shift amount, not SEW. 2. Use 128bit to store temporary result to handle shift = 63 case in rv64 Signed-off-by: Albert Ou <aou@eecs.berkeley.edu> Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	7 years ago
Albert Ou	590abe0960	rvv: fix INT_ROUNDING compliance * round-to-nearest-even: In the case that result[gb] = 0, the result should still be rounded up if result[gb-1] != 0 && result[gb-2:0] != 0 (the usual round-to-nearest behavior outside of the tiebreaker). * round-down: Since all uses of INT_ROUNDING() are immediately followed with a right shift by gb, clearing the lower bits is unnecessary. * round-to-odd: The LSB should be OR'd only if result[gb-1:0] != 0. Signed-off-by: Albert Ou <aou@eecs.berkeley.edu>	7 years ago
Chih-Min Chao	b9d9e1ebd0	rvv: remove configuable tail-zero tail zero feature has been removed after v0.8-draft Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	7 years ago
Chih-Min Chao	df85f7fbe4	rvv: fix redsum/vmv for non-tail-zero case Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	7 years ago
Chih-Min Chao	3fc52f5989	rvv: fix vmv.x.s signed-ext issue Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	7 years ago
Chih-Min Chao	530b2d1d58	rvv: fix floating-point exception for comparison don't use quiet api Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	7 years ago
Chih-Min Chao	a6dfd4e40f	rvv: remove vmford has been removed in https://github.com/riscv/riscv-v-spec/pull/249 Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	7 years ago
Andrew Waterman	3db3d4b122	Merge pull request #320 from zeldin/byteorder Implement support for big-endian hosts	7 years ago
Marcus Comstedt	b3c656629e	Whithhold BE ELF loading until BE target support is available	7 years ago
Marcus Comstedt	f437e6a4e9	Implement support for big-endian hosts	7 years ago
Scott Johnson	5652b9dd62	Initialize histogram_enabled and log_commits_enabled in constructor (#354 ) Otherwise they are left uninitialized and causing bizarre reproducibility problems in my application.	7 years ago
Luís Marques	66bf6ffa87	Catch polymorphic exceptions by reference (#352 )	7 years ago
Nick Knight	26026529e0	Stop loading "past the end" of the vector. (#351 )	7 years ago
Andrew Waterman	fb27391bf6	Add user write permissions to installed files	7 years ago
Andrew Waterman	e10f44738b	Enforce 2^56-bit physical address limit It's very difficult to encounter this (need to manually place a device or memory at very high addresses), but it is technically a Spike bug.	7 years ago
Andrew Waterman	bbe881f3c5	Speed up compilation of disasm.cc, especially in clang	7 years ago
Andrew Waterman	7cdcdfb01c	update changelog	7 years ago
fborisovskii	9443c1dbac	Fixed match trigger MATCH_NAPOT case. (#335 ) Mask calculation was not in consistency with debug spec. Watch debug spec. 5.2.7 match field overview and debug spec. B.9 fourth example. Mask should not cover LSB zero bit. Also there is a way to make it simplier: reg_t mask = ~(((~state.tdata2[i]) - 1) ^ ~state.tdata2[i]);	7 years ago

1 2 3 4 5 ...

1059 Commits (sodor) All Branches Search

1059 Commits (sodor)

All Branches