1583b7a9e2
[xcc, sim] replaced ble/bleu with bge/bgeu
This will simplify control logic (since every branch has a logical inverse)
16 years ago
19b59dd9a0
[sim] renamed sllv to sll (same for other shifts)
16 years ago
86ab285710
[xcc, sim] moved shamt field and renamed shifts
16 years ago
ab2da3ad68
[xcc, sim] branches now are next-PC-based, not PC-based
16 years ago
8edc1451b2
[xcc] fixed broken 32-bit FP ABI
16 years ago
9bd1c58531
[sim, xcc] Added mffh.d/mtflh.d; fixed FP ABI for 32-bit
16 years ago
b3dac377a1
[sim, pk] cleaned up exception vectors and FP exc flags
16 years ago
5b9b36def0
[opcodes,xcc,sim] mffh.d,mtfh.d added (broken commit)
16 years ago
05b409f48d
[opcodes,sim,xcc] move opcodes for 3 source instructions
16 years ago
a71855cfd6
Revert "[xcc, sim] added slei/sleui in lieu of slti/sltiu"
This reverts commit bf5406d4df625678bc6ec20ce1d48541541dba54.
We found a clever way to efficiently implement slti/sltiu despite the
reversed operands. The trick is because of the following fact:
(a < b) === !(b <= a) === !(b-1 < a)
So just turn off the carry-in when doing the subtraction for the comparison.
16 years ago
5c88aa157b
Merge branch 'master' of /project/eecs/parlab/git/projects/riscv
Conflicts:
sim/riscv/insns/mtpcr.h
sim/riscv/processor.cc
16 years ago
64ec648761
[pk, sim] added interrupt support to sim; added timer interrupt
16 years ago
a9176ab510
[sim] add while to interactive_until
16 years ago
9beab4ff43
[sim] change applink for tohost/fromhost (forgot one file)
16 years ago
3af5e6b1a5
[sim] change applink for tohost/fromhost
16 years ago
c82197c593
[xcc, sim] added slei/sleui in lieu of slti/sltiu
Rationale was that since we have the datapath for rc = (ra < rb),
it's straightforward to also add rc = !(imm < rb) = (rb <= imm).
16 years ago
0771c7b017
[sim] yet another fix stdint.h __STDC_LIMIT_MACROS problem
16 years ago
e460324b89
[sim] fix stdint.h __STDC_LIMIT_MACROS problem
16 years ago
8f2695a050
[sim, xcc] branches now have 2-byte-aligned displacements
This will facilitate 16-bit instructions later on
16 years ago
6df5eaaea8
[sim, xcc] added PCRs to replace k0 and k1
16 years ago
46697c22d4
[sim, xcc] bthread threading model exposed; insn encoding cleaned up
16 years ago
3fb39c1739
[sim] fixed bug in msub.d; added ability to print FPRs in debug mode
16 years ago
4ef2c87da8
[sim] added atomic memory operations
16 years ago
2ad48949b9
[xcc] argc/argv work for 32b programs
Some patch-up code runs as soon as the 32b version of crt1 begins running
that massages the pointers accordingly.
16 years ago
f04bbaa997
[sim] privileged mode support for 32-bit operation
16 years ago
3e18d4ccc0
[xcc,sim] added fused multiply-add and its cousins
16 years ago
d81bcf723e
[xcc,sim] Eliminated slori instruction
the "li" macro in RISC-V assembly isn't as efficient anymore for 64b
constants, and "la" doesn't work for 64b addresses with ".set noat".
But it's worth it to remove an ugly instruction.
16 years ago
bb7667a4d1
[pk,fesvr] improved proxykernel build system
Now uses a modified MCPPBS. Add --host=riscv to configure path.
Front-end server now just searches PATH for riscv-pk, so just install the pk
to somewhere in your path.
16 years ago
50ec828baf
[sim] integrated SoftFloat-3 with ISA sim; removed SoftFloat-2b
16 years ago
b46f178e58
[sim] specialized softfloat for riscv
16 years ago
9ba7af90cc
[sim] added riscv folder to softfloat
16 years ago
932ec48ad5
[sim] added SoftFloat-3 source
16 years ago
2d75bf71bb
[xcc,sim] implement FP using softfloat
The intersection of the Hauser FP and MIPS FP is implemented.
16 years ago
d9170d6002
[sim] removed unused elf loader
16 years ago
cf2bb15395
[sim] added softfloat
16 years ago
c12327f15c
[sim,xcc] Added first few Hauser FP insns (sign-injection)
Also updated FPmove test case to test negation and moving between FP regs
16 years ago
ae3bcd0a39
[sim] Bug fixes in shifts, plus a new test case
16 years ago
7134cf8d9e
[xcc] Removed ctc1, cfc1 instructions; added fp move test case
16 years ago
40998b4479
[xcc,pk,sim] Added first part of FP support
In particular, FP loads, stores, and moves now work.
16 years ago
6b5af53e2b
[sim,xcc] removed sll32/srl32/sra32 opcodes
These instructions handled static shift amounts >= 32. Since we have
a 6-bit shift amount field, these opcodes are no longer necessary.
16 years ago
5ff63bcd79
[pk,sim,xcc] Renamed instructions to RISC-V spec
All word-sized arithmetic operations are now postfixed with 'w',
and all double-word-sized arithmetic operations are no longer
prefixed with 'd'. mtc0/mfc0 are removed and replaced with
mfpcr/mtpcr/mwfpcr/mwtpcr.
16 years ago
864c3ef8ac
[gcc] generate code for complex branches
16 years ago
e8125348b3
[sim,xcc] Changed instruction format to RISC-V
Massive changes to gcc, binutils to support new instruction encoding.
Simulator reflects these changes.
16 years ago
133806b398
[sim] various fixes to get the sim work with the fesvr
16 years ago
ceb91dab9c
[pk,sim] removed cop0 console i/o support
16 years ago
d2c5b5c159
[pk,sim] first cut of appserver communication link
16 years ago
7a38f87432
[pk,sim] added temporary "exit" functionality
16 years ago
01c01cc36f
Reorganized directory structure
Moved cross-compiler to /xcc/ rather than /
Added ISA sim in /sim/
Added Proxy Kernel in /pk/ (to be cleaned up)
Added opcode map to /opcodes/ (ditto)
Added documentation to /doc/
16 years ago
Andrew Waterman
Yunsup Lee
Andrew Waterman