40cc0837cf
Actually inline load_fast/store_fast for clang/ARM
4 years ago
c8bceaefce
Simplify handling of misaligned loads/stores
4 years ago
d392e69f96
Fix trigger store priority.
Fixes the other half of #971 .
Compared the start of this set of changes, it now takes 11% longer to
run the towers benchmark (with 22 discs).
4 years ago
1c31a61269
Make templated store_fast() for use with store_func()
Easier to read, maintaing, compiler errors, etc.
4 years ago
37fe50b5ed
Don't check alignment before load_slow_path()
With this change, #971 is resolved for loads.
4 years ago
894ab32c66
Add require_alignment to load_slow_path().
I haven't tested unaligned accesses, nor different endianness.
4 years ago
5557067471
Turn load_fast() from macro into template
Easier to edit, better error messages from compiler, etc.
4 years ago
1a69427d96
Check early for trigger address in fast load_func()
4 years ago
5e9115a0e2
Use `size` variable consistently.
Slightly more readable than sizeof(type##_t) everywhere.
4 years ago
f8874bf55d
Check address for triggers before the access happens.
Only in slow path right now.
4 years ago
2b43192972
Use idiomatic iteration.
4 years ago
1890710e93
Add memory_access_match() to triggers.
In preparation for checking accesses before they happen, when we only
know the address and not the data.
4 years ago
32eeb5a2b2
Merge pull request #1003 from vogelpi/include-headers
Include recently added headers in riscv/riscv.mk.in
4 years ago
a59c44eb46
Include recently added headers in riscv/riscv.mk.in
4 years ago
e94d843e8b
Merge pull request #997 from riscv-software-src/simplify-decode_insn
Simplify decode_insn and insn_desc_t
4 years ago
78dfe62633
Fix disassembly of custom instructions that overlap standard ones ( #999 )
Iterate over the instruction chains in reverse order, prioritizing
the last call to `disassembler_t::add_insn`.
To preserve behavior for the standard instructions, reverse the order
in which we add instructions in the `disassembler_t` constructor.
Supersedes #995 .
4 years ago
ff645fb4eb
Disassemble Zicbop/Zihintpause HINT instructions ( #1000 )
We do not condition them on Zicbop/Zihintpause because,
definitionally, all implementations provide them.
4 years ago
918cba10e1
Update README to reflect recently added extensions
4 years ago
500d987d87
Add missing Zicbom and Zicbop extensions to disassembler fallback
4 years ago
2bf4c8c3df
Add missing Q, H, and Svinval extensions to disassembler fallback
4 years ago
e66e2e2b09
Remove now-unnecessary null check from decode_insn
Fixes bug introduced in 5b7cdbe1cf
4 years ago
0676421e93
Assert that nullptrs can't make their way into the instructions list
4 years ago
68b20a9b8a
Remove insn_func_t::supported field
The field is rendered unnecessary by 11f5942b7d750f008e72
4 years ago
11f5942b7d
Don't register instructions that aren't supported
These add to the length of the instruction list without providing
an apparent benefit.
4 years ago
8ed65cdc51
Merge pull request #992 from rbuchner-aril/rb-pbmte
Fix for issue #990 , implements the PBMTE bit in the henvcfg /menvcfg reisters
4 years ago
ccfeaa9973
Check for reserved PBMT values during tablewalks and fault if found
See #990 .
4 years ago
996634f0be
Switch from checking for SVPBMT extension to checking *ENVCFG values during tablewalks
Fix issue #990 .
4 years ago
ea70a9359d
Add PBMTE bit to menvcfg and henvcfg mask values
Also make PBMTE set on reset for backward compatibility.
Since before Spike proceeded as if these bits were set if the extension was enabled.
4 years ago
fc35f34fd0
Change henvcfg csr to a henvcfg_csr_t
To do so implemented henvcfg_csr_t.
henvcfg.PBMTE will be read only 0 if menvcfg.PBMTE = 0.
4 years ago
b19990805f
Merge pull request #994 from chihminchao/rvv-misc-2022-05-11
rvv: fix the checking eew and elen for index load
4 years ago
08afafccfd
rvv: fix the checking eew and elen for index load
eew of index register can't be larger than elen
ex:
elen = 32, vloxei64.v is illegal
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
4 years ago
3099c33d15
Merge pull request #988 from riscv-software-src/factor-out-macros
Factor out P and V extension macros into their own headers
4 years ago
615de147a2
Factor out P extension macros into their own header
No functional change.
4 years ago
15a370bde2
Factor out V extension macros into their own header
No functional change.
4 years ago
8e8af2659a
Merge pull request #983 from soberl/epmp_updates_2
Implement Smepmp extension
4 years ago
6d2549d2ad
Append smepmp extension 1.0 to the feature list
4 years ago
b0fdd88d26
Update pmpaddr_csr_t::access_ok() for ePMP on matching regions
4 years ago
115a9b3dc2
Update mmu_t::pmp_ok() for ePMP in case matching region is not found
4 years ago
af500657c3
Update csr access rules for ePMP on pmpaddr and pmpcfg
4 years ago
84a98f6f71
Implement the new csr mseccfg for ePMP as dummy
4 years ago
89745abd8c
Merge pull request #985 from riscv-software-src/trigger_hit
Implement mcontrol.hit bit
4 years ago
a8245e92fb
Fix the padding of register names in the log ( #987 )
This fix print x5 as "x5 ", instead of "x 5".
4 years ago
8f46a28436
Linking spike_dasm misses libriscv.a dependance ( #986 )
Whereas spike-dasm.cc now instanciates an isa_parser_t,
the dependance on libriscv.a has become unconditional.
4 years ago
62ecca6f8a
Use MCONTROL_TYPE_MATCH macro instead of 2
4 years ago
85fbd75d44
Implement mcontrol trigger hit bit.
4 years ago
1df65613df
Add missing description of --dtb in --help message
4 years ago
1cfffeda1e
Add zknd zkne zknh zksed zksh disassembly support ( #979 )
4 years ago
f2f6037fea
Remove mcontrol_t.h
It was removed from the spec a long time ago.
4 years ago
1dbcee7d97
Merge pull request #978 from rbuchner-aril/amo-order-change-patch
Bug Fix for bug introduced in PR #976
4 years ago
16413646bb
Remove maskmax as a variable.
4 years ago
Andrew Waterman
Tim Newsome
Pirmin Vogel
Ryan Buchner
Chih-Min Chao
Scott Johnson
soberl
Shaked Flur
jmonesti
Yan