riscv-isa-sim

Commit Graph

Author	SHA1	Message	Date
hdinc	d62d3075a2	ns16550.cc : fix handling clear rx/tx FIFO requests. Signed-off-by: hdinc <macellan091@gmail.com>	1 year ago
Hao	9950cb3d59	fix: check ext_str size when ext = zve* `zve` = "zve{32, 64}{x, f, d}", size of `zve` must be 6. Signed-off-by: Hao <58808837+ha0lyu@users.noreply.github.com>	1 year ago
Andrew Waterman	113ef64f67	Merge pull request #2044 from klingaard/klingaard/issue_2038_quad_logging_store_issue For writes + logging, if len > 8 bytes, break up the memory log	1 year ago
Knute Lingaard	4ecd2e7e79	Merge branch 'master' into klingaard/issue_2038_quad_logging_store_issue	1 year ago
Andrew Waterman	0fa8e0c710	Merge pull request #2040 from mmhus/mmhus/take-sireg-case-out-of-switch Sireg is not in the sireg_csrs[] list, so needs to be checked outside… #2041	1 year ago
Knute Lingaard	09e4d6d089	Fixed issues with logging	1 year ago
Muhammad Moiz Hussain	5063dcb8ea	Sireg is not in the sireg_csrs[] list, so needs to be checked outside of the switch-case	1 year ago
Andrew Waterman	2794373c62	Merge pull request #2042 from riscv-software-src/register-device Don't include built-in devices in mmio_device_map	1 year ago
Andrew Waterman	8da8b6a34d	Don't include built-in devices in mmio_device_map Only use mmio_device_map for plugin devices. This fixes a collision caused by multiple static initializers if Spike depends on a library that depends on libriscv.so.	1 year ago
Andrew Waterman	c61e4bccce	Remove brittle reliance on ordering of factory table	1 year ago
Andrew Waterman	483e01d486	Merge pull request #2037 from riscv-software-src/2036-redux Only support 56-bit PMP and ATP addresses	1 year ago
Andrew Waterman	352597c4cf	Remove MAX_PADDR_BITS It isn't used anymore.	1 year ago
Andrew Waterman	a89875689e	Only support 56-bit PMP addresses As mandated by the ISA spec.	1 year ago
Andrew Waterman	72e8cad123	Implement processor_t::paddr_bits correctly It wasn't being called anywhere, so the 50- vs. 56-bit discrepancy never manifested.	1 year ago
Andrew Waterman	94beb3c026	Remove physical address checks in sim_t Processors are responsible for validating physical addresses; the bus is only responsible for making some device lives at a given address.	1 year ago
Andrew Waterman	3e58f5ef62	Merge pull request #2033 from i2h2/vs-interrupts AIA: vstopi should only be used for AIA-extended interrupts	1 year ago
Ian Huang	b6f4d246bc	AIA: vstopi should only be used for AIA-extended interrupts VSEIP/VSTIP/VSSIP should come in through the non-SSAIA path. vstopi will be used to throw VTI and IID > 13 interrupts.	1 year ago
Andrew Waterman	2a0bb5f543	Merge pull request #2029 from theOfficeCat/README.md-zfa Add Zfa to README.md	1 year ago
Aike Gilabert Gámez	b9e1d219c8	Add Zfa to README.md Signed-off-by: Aike Gilabert Gámez <aikegilabert@gmail.com>	1 year ago
Andrew Waterman	965547260a	Merge pull request #2025 from mslijepc/mslijepc_20250702_additional-files-riscvmkin added jtag_dtm and remote_bitbang to riscv_install_hdrs	1 year ago
Andrew Waterman	4c932cff7a	Merge pull request #1882 from fk-sc/fk-sc/mprven-support Add DCSR.MPRVEN support	1 year ago
mslijepc	d2cf8b0419	added jtag_dtm and remote_bitbang to riscv_install_hdrs	1 year ago
Farid Khaydari	9b2a1d6c81	Add DCSR.MPRVEN support Adds DCSR.MPRVEN bit support, as specified in RISC-V External Debug Support Version 1.0.0-rc4 (https://github.com/riscv/riscv-debug-spec/releases/tag/1.0.0-rc4, see 4.9.1 Debug Control and Status). This bit allows to enable hardware virtual address translation when memory access is initiated by the debugger (see 4.1 Debug Mode, clause 2). This change: * Increases debug specification coverage, allows more detailed testing of external debuggers with Spike. * Decreases the number of required abstract commands to read virtual memory thus improving the user experience. Commit's changes: * Added MPRVEN field to DCSR register * Updated debug_rom.S to turn off MPRVEN on memory access To avoid unwanted address translation while debug_rom.S executed DCSR.MPRVEN bit has to be cleared before and restored after access. Signed-off-by: Farid Khaydari <f.khaydari@syntacore.com>	2 years ago
Andrew Waterman	ba54a6015f	Merge pull request #2022 from aap-sc/aap-sc/another_unused_variable_warning remove unused EGS constant from vsm4r_vs handler	1 year ago
Parshintsev Anatoly	7f8aa45514	remove unused EGS constant from vsm4r_vs handler The macro require_vsm4_constraints defines EGS once again (shadowing the definition of this constant, since it introduces a new scope). This renders the original definition as "unused", causing warning during compilation.	1 year ago
Andrew Waterman	14670706c1	Merge pull request #2021 from aap-sc/aap-sc/unused_write_warning_fixup fixed warnings about unused parameter when csrs.h file is included	1 year ago
Parshintsev Anatoly	380efd9b80	fixed warnings about unused parameter when csrs.h file is included	1 year ago
Andrew Waterman	70687ccf41	Merge pull request #2015 from binno/fix_mseccfg_write Continue mseccfg write operation even without PMP setting	1 year ago
Andrew Waterman	79907ef8d3	Merge pull request #2014 from binno/fix_vs_exception_delegation Adjust vsdeleg from VSSIP to SSIP interrupt occurred	1 year ago
Andrew Waterman	0f8875631a	Merge pull request #2013 from binno/aia_fix Ensure AIA extension enabled when accessing hvictl	1 year ago
Binno	5d0ab7e1f0	Check H extension enabled when accessing hvictl Signed-off-by: Binno <binno.shen@sifive.com>	1 year ago
Binno	c17d206089	Continue mseccfg write operation even without PMP setting Signed-off-by: Binno <binno.shen@sifive.com>	1 year ago
Binno	46fdf37d65	Adjust vsdeleg from VSSIP to SSIP interrupt occurred Signed-off-by: Binno <binno.shen@sifive.com>	1 year ago
Binno	7c01135f5b	Ensure AIA extension enabled when accessing hvictl Signed-off-by: Binno <binno.shen@sifive.com>	1 year ago
Andrew Waterman	065950a045	Merge pull request #2010 from jmonesti/perf.aia Performance: processor_t::take_interrupt() should check EXT_SSAIA	1 year ago
Jean-François Monestier	4dfba258d9	Performance: processor_t::take_interrupt() should check EXT_SSAIA The implementation of SMAIA and SSAIA extensions incurs a significant performance penalty. Better check whether EXT_SSAIA is enabled before accessing the considered CSR's Cf. commit # `ddc025a80d` commit # `a6708d5588`	1 year ago
Andrew Waterman	5cb0a97677	Merge pull request #2008 from HaochenGui/all-one-agnostic Bypass masked-off elements for viota	1 year ago
Haochen Gui	1ec477fffe	Bypass masked-off elements for viota * riscv/insns/viota_m.h: Bypass masked-off elements.	1 year ago
Andrew Waterman	4f1d8abf39	Merge pull request #2005 from riscv-software-src/ziccid Implement Ziccid extension	1 year ago
Andrew Waterman	833ab91894	Reduce perf impact of Ziccid Modifications are expected to be uncommon, so don't flush the I$ quite so often.	1 year ago
Andrew Waterman	cce834e437	Support Ziccid extension	1 year ago
Andrew Waterman	b6a061b683	Support Ziccif extension	1 year ago
Andrew Waterman	99194302df	Merge pull request #2004 from jmonesti/bugfix-cm.jalt Bugfix cm.jalt	1 year ago
Jean-François Monestier	2554792041	Bugfix cm.jalt	1 year ago
Andrew Waterman	5894afaaa5	Merge pull request #2001 from Steven-Li-Xiaogang/master menvcfg.CDE is defined by Smcdeleg not Smcsrind	1 year ago
steven	937e812212	menvcfg.CDE is defined by Smcdeleg	1 year ago
Andrew Waterman	4c870d063d	Merge pull request #1998 from mingtians/update-readme Update README with Zimop extension	1 year ago
mingtians	05f2a66564	Update README with Zimop extension	1 year ago
Andrew Waterman	d28344a1e7	Merge pull request #1988 from binno/pr-aia AIA: Implement Smaia/Ssaia extension	1 year ago
Andrew Waterman	a3dbcbadf3	Merge pull request #1997 from riscv-software-src/fix-1996 Partially revert #1987 to fix regrssion in vsra.vi and vssra.vi	1 year ago

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4151 Commits (master)

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