3f144b12ed
[xcc, sim, pk] link register is now x1
16 years ago
68f81d8f48
[opcodes, pk, sim, xcc] made jumps shorter and PC-relative
16 years ago
63844a7558
[sim] removed unnecessary trap in mfcr instruction
16 years ago
5f0b1c3e7b
[sim,xcc] fixed minor bugs related to tp/cr29
16 years ago
78bc7d9885
[pk,sim,xcc] get rid of at register, introduce tp register
16 years ago
2c9a832352
[sim,xcc,pk,opcodes] static rounding modes for FP insns
Now, you can either use the RM in the FSR or specify it in the insn.
(Except for FP->int; no dynamic for that.)
16 years ago
8456c1e923
[pk, sim] added FPU emulation support to proxy kernel
16 years ago
ab928baadb
[sim] made softfloat files C instead of C++
16 years ago
d3cb781e16
[sim] added writeback tracing
16 years ago
9222fb8ab8
[xcc] modified opcodes for better FP decode mapping
16 years ago
9817b7be3d
[opcodes] added code field back to syscall/break
16 years ago
2d58d46c89
[xcc] removed CEXC field from FSR
16 years ago
a359d7b81a
[xcc,sim] eliminated vectored traps
now, the evec register holds the address that all traps vector to,
and the cause register is set with the trap number.
16 years ago
fcdd030cbe
[sim, xcc] changed cvt/trunc to use GPRs for int args
this way, we don't have to futz with storing integers in recoded
floating-point registers. too bad we lose some decoupling.
16 years ago
04fa9f8603
[xcc, sim] mff now uses rs2 for data
this is symmetric with fp stores, so we only need one decoding pipe
16 years ago
68ddbd26c3
[opcodes, sim, xcc] added mffl.d instruction
...to be used instead of mff.s when doing int -> DP FP moves on a 32-bit cpu
16 years ago
ee7cb7243e
[xcc, sim] eliminated zero-extended immediates
This is a big commit because it involved rewriting gcc's algorithm for
generating constants.
16 years ago
c28cb729f9
[sim] fixed bug in which shift operands were reversed
16 years ago
cbefaf68c7
[xcc, sim] changed instruction format so imm12 subs for rs2
16 years ago
1583b7a9e2
[xcc, sim] replaced ble/bleu with bge/bgeu
This will simplify control logic (since every branch has a logical inverse)
16 years ago
19b59dd9a0
[sim] renamed sllv to sll (same for other shifts)
16 years ago
86ab285710
[xcc, sim] moved shamt field and renamed shifts
16 years ago
ab2da3ad68
[xcc, sim] branches now are next-PC-based, not PC-based
16 years ago
8edc1451b2
[xcc] fixed broken 32-bit FP ABI
16 years ago
9bd1c58531
[sim, xcc] Added mffh.d/mtflh.d; fixed FP ABI for 32-bit
16 years ago
b3dac377a1
[sim, pk] cleaned up exception vectors and FP exc flags
16 years ago
5b9b36def0
[opcodes,xcc,sim] mffh.d,mtfh.d added (broken commit)
16 years ago
05b409f48d
[opcodes,sim,xcc] move opcodes for 3 source instructions
16 years ago
a71855cfd6
Revert "[xcc, sim] added slei/sleui in lieu of slti/sltiu"
This reverts commit bf5406d4df625678bc6ec20ce1d48541541dba54.
We found a clever way to efficiently implement slti/sltiu despite the
reversed operands. The trick is because of the following fact:
(a < b) === !(b <= a) === !(b-1 < a)
So just turn off the carry-in when doing the subtraction for the comparison.
16 years ago
5c88aa157b
Merge branch 'master' of /project/eecs/parlab/git/projects/riscv
Conflicts:
sim/riscv/insns/mtpcr.h
sim/riscv/processor.cc
16 years ago
64ec648761
[pk, sim] added interrupt support to sim; added timer interrupt
16 years ago
a9176ab510
[sim] add while to interactive_until
16 years ago
9beab4ff43
[sim] change applink for tohost/fromhost (forgot one file)
16 years ago
3af5e6b1a5
[sim] change applink for tohost/fromhost
16 years ago
c82197c593
[xcc, sim] added slei/sleui in lieu of slti/sltiu
Rationale was that since we have the datapath for rc = (ra < rb),
it's straightforward to also add rc = !(imm < rb) = (rb <= imm).
16 years ago
0771c7b017
[sim] yet another fix stdint.h __STDC_LIMIT_MACROS problem
16 years ago
e460324b89
[sim] fix stdint.h __STDC_LIMIT_MACROS problem
16 years ago
8f2695a050
[sim, xcc] branches now have 2-byte-aligned displacements
This will facilitate 16-bit instructions later on
16 years ago
6df5eaaea8
[sim, xcc] added PCRs to replace k0 and k1
16 years ago
46697c22d4
[sim, xcc] bthread threading model exposed; insn encoding cleaned up
16 years ago
3fb39c1739
[sim] fixed bug in msub.d; added ability to print FPRs in debug mode
16 years ago
4ef2c87da8
[sim] added atomic memory operations
16 years ago
2ad48949b9
[xcc] argc/argv work for 32b programs
Some patch-up code runs as soon as the 32b version of crt1 begins running
that massages the pointers accordingly.
16 years ago
f04bbaa997
[sim] privileged mode support for 32-bit operation
16 years ago
3e18d4ccc0
[xcc,sim] added fused multiply-add and its cousins
16 years ago
d81bcf723e
[xcc,sim] Eliminated slori instruction
the "li" macro in RISC-V assembly isn't as efficient anymore for 64b
constants, and "la" doesn't work for 64b addresses with ".set noat".
But it's worth it to remove an ugly instruction.
16 years ago
bb7667a4d1
[pk,fesvr] improved proxykernel build system
Now uses a modified MCPPBS. Add --host=riscv to configure path.
Front-end server now just searches PATH for riscv-pk, so just install the pk
to somewhere in your path.
16 years ago
50ec828baf
[sim] integrated SoftFloat-3 with ISA sim; removed SoftFloat-2b
16 years ago
b46f178e58
[sim] specialized softfloat for riscv
16 years ago
9ba7af90cc
[sim] added riscv folder to softfloat
16 years ago
Andrew Waterman
Yunsup Lee
Andrew Waterman
Andrew Waterman