riscv-isa-sim

Commit Graph

Author	SHA1	Message	Date
Andrew Waterman	63c60931bc	Merge pull request #2204 from mmhus/mmhus/mireg-sireg-fixes Mmhus/mireg sireg fixes #2188, #2202, #2203	7 months ago
muhammad.moiz.hussain	49dea04810	fixed smcdeleg to be limited to, holds a value in the range 0x40-0x5F, from priv AIA section 9.1	7 months ago
muhammad.moiz.hussain	88783bf6e1	changed minstret to instret and mcycle to cycle	7 months ago
muhammad.moiz.hussain	2e7042897d	when AIA throw virt intruction exception and V=1 & vs-mode, otherwise throw illegal instruction exception	7 months ago
Andrew Waterman	59b2c834a4	Merge pull request #2193 from mslijepc/mslijepc_20251224_zicclsm added support for zicclsm	7 months ago
mslijepc	d6a5e90c40	removed cfg.misaligned option	7 months ago
Andrew Waterman	45fe6c110a	Merge pull request #2197 from omerguzelelectronicguy/master remove unnecessary dtb to dts operation	7 months ago
Andrew Waterman	1f92dadc89	Merge pull request #2161 from fkhaidari/fk/trig-algo-mod Update trigger behavior for memory accesses to match recommended debug specification behavior	7 months ago
Ömer Güzel	9b18d004f3	unnecessary dtb to dts operation removed	7 months ago
Farid Khaydari	06fd4d8526	Update trigger behavior for memory accesses to match recommended debug specification behavior According to the debug specification (select bit description): 0 (address): There is at least one compare value and it contains the lowest virtual address of the access. In addition, it is recommended that there are additional compare values for the other accessed virtual addresses match. (E.g. on a 32-bit read from 0x4000, the lowest address is 0x4000 and the other addresses are 0x4001, 0x4002, and 0x4003.) 1 (data): There is exactly one compare value and it contains the data value loaded or stored, or the instruction executed. Any bits beyond the size of the data access will contain 0. Previously, when select bit was 0, Spike did not follow the recommendation and provided only 1 matching value to the trigger module. This change modifies the behavior to the recommended one. The implementation follows the debug specification recommendation. Signed-off-by: Farid Khaydari <f.khaydari@syntacore.com>	8 months ago
Andrew Waterman	f0cc387904	Merge pull request #2194 from riscv-software-src/fix-2192 Remove declaration for undefined function	8 months ago
Andrew Waterman	b62fad4387	Remove declaration for undefined function Fixes #2192	8 months ago
mslijepc	5cf8c829d2	added support for zicclsm	8 months ago
steven	6aae741fd7	register indirection CSRs 'iprio0~iprio15' when Smaia/Ssaia supported	8 months ago
Andrew Waterman	d4cd5e3118	Merge pull request #2189 from Steven-Li-Xiaogang/master Raise an illegal-instruction exception upon accessing sireg* (really vsireg*) from VS-mode, while vsiselect holds a value unimplemented	8 months ago
steven	b9dd2e5d84	Better to raise an illegal-instruction exception upon accessing sireg* (really vsireg) from VS-mode, while vsiselect holds a value unimplemented.	8 months ago
Andrew Waterman	fd72ee2d3e	Merge pull request #2187 from riscv-software-src/2186-redux Fix infinite loop due to integer overflow in PMP check	8 months ago
Andrew Waterman	3b9bfa858b	Fix infinite loop due to integer overflow in PMP check	8 months ago
Andrew Waterman	482430178d	Merge pull request #2182 from mmhus/mmhus/reorder_hstateen0_check_smcdeleg #2082 Reorder hstateen0 check for smcdeleg	8 months ago
Andrew Waterman	9759fef739	Merge pull request #2180 from mslijepc/mslijepc_20251210_softfloat-declaration softfloat: Add f32_to_i8 and f32_to_ui8 function declarations	8 months ago
mslijepc	6fda58b86a	softfloat: Add f32_to_i8 and f32_to_ui8 function declaration	8 months ago
Muhammad Moiz Hussain	eef599cc19	#2082 Reorder hstateen0 check for smcdeleg	8 months ago
Andrew Waterman	76e891cab0	Merge pull request #2183 from riscv-software-src/fix-ci Move CI to MacOS 15	8 months ago
Andrew Waterman	f49a485c02	Move CI to MacOS 15 The MacOS 13 runners have been retired.	8 months ago
Andrew Waterman	abb0d98738	Merge pull request #2166 from Steven-Li-Xiaogang/master Fix VS-mode check for sireg* (really vsireg*) CSRs	8 months ago
Andrew Waterman	59bf54676e	Merge pull request #2176 from riscv-software-src/fix-flq-fsq-big-endian Fix Q extension on big-endian targets	8 months ago
Andrew Waterman	57fb2facf3	Fix Q extension on big-endian targets The previous routines always stored the low-order bits into the low-order doubleword, which is only correct on little-endian targets.	8 months ago
Andrew Waterman	e04e7f944c	Disable Q extension unless uint128_t is defined	8 months ago
Andrew Waterman	6963ea936a	Merge pull request #2175 from riscv-software-src/improve-mmu-impl Clean up VA size handling	8 months ago
Andrew Waterman	1bf835816a	Clean up VA size handling Representing the VA size as a feature set rather than an integer allows for internal inconsistency and is inelegant.	8 months ago
Andrew Waterman	fd604be778	Merge pull request #2171 from riscv-software-src/fix-svukte Fix Svukte implementation	8 months ago
Andrew Waterman	62d64ef6bd	Fix Svukte implementation - Change polarity of svukte_qualified to match ISA spec - Avoid address dependence of svukte_qualified, per ISA spec - Move address check to separate routine	8 months ago
Andrew Waterman	3d97c3e1a2	Merge pull request #2153 from chihminchao/enhance-zve Enhance zve	8 months ago
Andrew Waterman	59c1f33ff5	Merge pull request #2170 from binno/spelp_fix SPELP field is defined only when S mode is enabled	8 months ago
Andrew Waterman	c6c3d29828	Merge pull request #2168 from riscv-software-src/simplify-opcode-map Simplify instruction fetch by getting rid of opcode cache	8 months ago
Binno	3e9e06b2cd	SPELP field is defined only when S mode is enabled Signed-off-by: Binno <binno.shen@sifive.com>	8 months ago
Chih-Min Chao	b59f916de9	zve: correct the constraint for widening and floating configuraiton Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	9 months ago
Chih-Min Chao	f364814542	zve: correct the requirement for convension Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	10 months ago
Chih-Min Chao	d1e34d021f	zve: some MUL operaiton are unavailable to zve64 Based on section 18.2 in spec "All Zve* extensions support all vector integer instructions (Section Vector Integer Arithmetic Instructions), except that the vmulh integer multiply variants that return the high word of the product (vmulh.vv, vmulh.vx, vmulhu.vv, vmulhu.vx, vmulhsu.vv, vmulhsu.vx) are not included for EEW=64 in Zve64." "All Zve extensions support all vector fixed-point arithmetic instructions (Vector Fixed-Point Arithmetic Instructions), except that vsmul.vv and vsmul.vx are not included in EEW=64 in Zve64*" Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	10 months ago
Chih-Min Chao	817a4d7800	zve: relax zvfhmin and zvfh Based on spec section 18.4 "The Zvfhmin extension depends on the Zve32f extension." section 18.5, "The Zvfh extension depends on the Zve32f and Zfhmin extensions." Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	10 months ago
Andrew Waterman	f7616ad7c2	Eliminate the opcode cache Just bucket the intruction lists, then search them. Simpler and faster.	9 months ago
Andrew Waterman	2ec106b785	Rebuild opcode map whenever ISA/logging changes This facilitates caching less info in the opcode cache.	9 months ago
Andrew Waterman	bac3747210	Merge pull request #2169 from riscv-software-src/snippy-tests-per-extension ci: auto-generate per extension snippy tests	8 months ago
Alexander Romanov	0f289394f3	ci: auto-generate per extension snippy tests This way adding new extension tests is as easy as adding 1 line script call and it is much harder to leave some instruction untested	8 months ago
Andrew Waterman	6392b9e60d	Merge pull request #2162 from chihminchao/fix-zvfofp4min-contraint zvfofp4min: fix shared contraint with v[zs]ext	8 months ago
Andrew Waterman	7d49ba7f60	Merge pull request #2163 from chihminchao/fix-double-trap Fix double trap	8 months ago
Andrew Waterman	46ef2ed8b3	Merge pull request #2167 from riscv-software-src/fix-zawrs-typo misc: fix typo in zawrs incompatible error	8 months ago
Alexander Romanov	f2a76d7a3d	misc: fix typo in zawrs incompatible error	8 months ago
steven	b4854c1493	Fix VS-mode check for sireg* (really vsireg*) CSRs	8 months ago
Chih-Min Chao	755ad71bb7	zvfofp4min: fix shared contraint with v[zs]ext Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	8 months ago

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