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arrv-sc-arrv-sc/snippy-tests

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dts_parsing

dynamic

eos18-bringup

factor-out-macros

fetch

fix-bf16

force-rtti

fp-encoding

heterogeneous_mc

hwachav4

increase-stack-size

itrigger-etrigger-cleanup

load_reservation_set_size

log-commits-faster

master

mmio-hack

mvp

no_progbuf

no_progbuf2

nolibfdt

optimized-chunk-size

p-ext-0.5.2

plctlab-plct-zce-fix2

plic-clint-endian

plic_uart_v1

priv-1.10

private-l1-caches

pte-info-and-delegation

remove-tests

rivosinc-etrigger_fix_exception_match

rva-profile-support

sanitize

simplify-misaligned

sodor

sparse-mem

speed2

speedup-hacks

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test

tmp

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v1.1.0

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4151 Commits (master)

 

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Author	SHA1	Message	Date
Andrew Waterman	e8e3a747d5	Dramatically simplify whole-register loads/stores This makes the vstart/VS handling identical to regular vector loads/stores	5 months ago
Andrew Waterman	ae1531c207	Merge pull request #2239 from riscv-software-src/fix-2238 Make minstretcfg/mcyclecfg privilege bits read-only zero as appropriate	5 months ago
Andrew Waterman	114be91bbe	Remove incorrect use of static variable It prevents modeling mixed RV32/RV64 systems.	5 months ago
Andrew Waterman	0714f0f588	Simplify masking of mnstatus bits when H is toggled	5 months ago
Andrew Waterman	6aa146d209	Simplify masking of medeleg bits when H is toggled	5 months ago
Andrew Waterman	cdca6411ad	Simplify masking of mhpmevent bits when H is toggled	5 months ago
Andrew Waterman	1d50ad3984	Make minstretcfg/mcyclecfg privilege bits read-only zero as appropriate	5 months ago
Andrew Waterman	68d4514685	Merge pull request #2236 from riscv-software-src/fix-2235 Don't error out if program buffer has size 0	5 months ago
Andrew Waterman	c73c3a1791	Merge pull request #2234 from hirooih/README.md-gdb-semihosting Updated “Debugging With Gdb” to use semihosting	5 months ago
Andrew Waterman	ab21eb0e4c	Merge pull request #2165 from FrancescoScappatura-Ax/dtb_discovery_feature DTB discovery feature	5 months ago
Andrew Waterman	5564ca81b7	Don't error out if program buffer has size 0 Resolves #2235	5 months ago
Hiroo HAYASHI	82742081e9	Updated “Debugging With Gdb” to use semihosting - make the sample program as a typical C program that uses the stack and semihosting (#155). - use the default crt0.o and linker script. Signed-off-by: Hiroo HAYASHI <24754036+hirooih@users.noreply.github.com>	2 years ago
Francesco Scappatura	2c94ea431e	DTB discovery feature	6 months ago
Andrew Waterman	b8eacc25b8	Merge pull request #2232 from riscv-software-src/fix-2230 Disallow delegation of misaligned-fetch exceptions when IALIGN=16	6 months ago
Andrew Waterman	4adab496a2	Disallow delegation of misaligned-fetch exceptions when IALIGN=16 Fixes #2230	6 months ago
Andrew Waterman	875a7ee66a	Merge pull request #2228 from abejgonzalez/patch-2 Modify in_bits to check in_valid before accessing	6 months ago
Abraham Gonzalez	78762796e8	Modify in_bits to check in_valid before accessing Signed-off-by: Abraham Gonzalez <abe.j.gonza@gmail.com>	6 months ago
Andrew Waterman	eb6586e3de	Merge pull request #2227 from riscv-software-src/fix-2221 Raise correct trap in U-mode on indirect CSRs when !mstateen.csrind	6 months ago
Andrew Waterman	aea74cb694	Raise correct trap in U-mode on indirect CSRs when !mstateen.csrind Fixes #2221	6 months ago
Andrew Waterman	98ccf030bb	Merge pull request #2221 from DymShanks/fix/vu-mode-sireg Fix: Enforce virtual_instruction trap for VU-mode indirect CSR access	6 months ago
DymShanks	49d1d2a802	Fix: Enforce virtual_instruction trap for VU-mode indirect CSR access	7 months ago
Andrew Waterman	7655ac0843	Merge pull request #2223 from riscv-software-src/fix-deps Regularize extension-dependency handling	6 months ago
Andrew Waterman	8b802199fb	Have Zabha imply extensions rather than erroring if not present	7 months ago
Andrew Waterman	5c142baf88	Have ZC* imply extensions rather than erroring if not present	7 months ago
Andrew Waterman	27ecd02d6b	Have Zvfofp4min imply extensions rather than erroring if not present	7 months ago
Andrew Waterman	1a2af0362e	Clean up handling of Zcf	7 months ago
Andrew Waterman	ac939da203	Have V imply extensions rather than erroring if not present	7 months ago
Andrew Waterman	466d1b0e4c	Have Z[v]fbfmin imply extensions rather than erroring if not present	7 months ago
Andrew Waterman	8b22afdbd9	Have Zvfhmin imply extensions rather than erroring if not present	7 months ago
Andrew Waterman	a91c0a9f51	Factor out add_extension method	7 months ago
Andrew Waterman	e9571d4498	Have Zfhmin imply extensions rather than erroring if not present	7 months ago
Andrew Waterman	715906f416	Have Zclsd imply extensions rather than erroring if not present	7 months ago
Andrew Waterman	978f96a992	Have Zicfiss imply extensions rather than erroring if not present	7 months ago
Andrew Waterman	9882cd202b	Zicfiss depends on Zaamo So, no need to check for Zaamo in the instruction definitions	7 months ago
Andrew Waterman	e7901f43aa	Don't log commits in snippy tests Doing so adds too much output to the CI logs.	6 months ago
Andrew Waterman	9cea90bd28	Merge pull request #2224 from riscv-software-src/add-vector-test Add simple vector extension test to CI	6 months ago
Andrew Waterman	52e6a75584	Echo CI commands to ease debugging	6 months ago
Andrew Waterman	6ff9d9ccd5	Add simple vector extension test to CI	6 months ago
Andrew Waterman	6dda4896cb	Merge pull request #2198 from riscv-software-src/fix-amocas-q Fix triggers for accesses wider than XLEN	7 months ago
Andrew Waterman	dfbd749842	Make reg_from_bytes a bit less gross I'd like to remove this routine eventually, but let's make it a bit less visually unappealing in the meantime.	7 months ago
Andrew Waterman	497e3d830d	DRY in logging code	7 months ago
Andrew Waterman	0f59a6dc75	Fix triggers for accesses wider than XLEN I believe that @en-sc's comment here is correct: https://github.com/riscv-software-src/riscv-isa-sim/pull/2161#discussion_r2564958203 Nevertheless, failing an assertion when someone sets a trigger on memory accessed by a wide access is not reasonable behavior for Spike. Better to do something that follows the principle of least surprise, despite the debug spec's lack of clarity on this point.	7 months ago
Andrew Waterman	b92958a9f1	Merge pull request #2216 from pointerliu/fix-tw-read csrs.cc: if no U-mode, mstatus.tw is read-only 0	7 months ago
pointerliu	4c10fbe07b	csrs.cc: if no U-mode, mstatus.tw is read-only 0	7 months ago
Andrew Waterman	efdaa08371	Merge pull request #2208 from riscv-software-src/remove-grevi Don't rely on definition of unratified bitmanip opcodes	7 months ago
Andrew Waterman	e532913fb3	Don't rely on definition of unratified bitmanip opcodes See https://github.com/riscv/riscv-opcodes/pull/401	7 months ago
Andrew Waterman	26aab67907	Clean up grevi/gorci/shfli/unshfli implementations No need for extra shamt variable.	7 months ago
Andrew Waterman	047b05cf7c	Merge pull request #2205 from Steven-Li-Xiaogang/master correct smcdeleg indirect CSRs address accessed via sireg*	7 months ago
steven	12e9a38efb	correct smcdeleg indirect CSRs address accessed via sireg*	7 months ago
Andrew Waterman	ce747bedbc	Merge pull request #2191 from Steven-Li-Xiaogang/master indirection CSRs 'iprio0~iprio15' are defined by Smaia/Ssaia extensions	7 months ago