16 B suffices to subsume all aligned accesses (including the Q extension).
Spike does not actually rely on this property, but in some real systems,
it is impractical to guarantee atomicity across cache lines.
4096 B suffices to prevent cache lines from spanning pages (which would
require multiple TLB accesses). This one is a bug fix, since we were
not performing multiple TLB accesses in this case.
The only slightly difficult thing here is that hartids will always
be considered "overridden" by the time we get to sim_t::sim_t (either
overridden by a command line argument, or overridden when we set
default hartids just before the constructor). To allow downstream code
to distinguish between "I picked IDs 0, 1, 2, 3 because the user asked
for 4 processors" and "The user explicitly asked for IDs 0, 1, 2, 3",
we have an extra explicit_hartids field.
We now parse to a std::vector<int> and then set the "hartids" variable
to the result.
There is a slight functional change here, in that if you pass
"--hartids 1,2,3 --hartids 4,5", you'll now get 2 cores with ids of
4,5 rather than 5 cores with ids of 1,2,3,4,5. This is what most tools
do with repeated command line arguments and I suspect the old
behaviour was actually by accident!
The motivation here is mostly to enable a refactoring where the memory
layout (sans allocated memory) gets passed to DTS/DTB code before we
ever allocate anything.
But it turns out to make merge_overlapping_memory_regions a bit
simpler, which is an added bonus.
This commit defines a "cfg_t" structure, which currently just holds
the initrd address range. It will be augmented in future commits to
hold other configuration arguments as well.
To represent a configuration argument, we define an arg_t base class.
This holds a current value, together with a flag that tells us whether
the value has been updated from the default. The idea is that in
future we're going to use that flag when reading a DTB file: if an
argument has actually been specified on the command line, we need to
take it into account; if not, we can ignore the default and use the
DTB file's supplied value.
This is a minor change, turning processor_t from a child class of
isa_parser_t into a class that contains an isa_parser_t as a field.
The point is that it is a step toward separating out
"configuration" (and ISA string parsing) from processor state. This
should be helpful for rejigging things so that we construct more from
a supplied device tree.
problem:
when the following memory region is specified
-m0x00410000:0x1000,
0x00410200:0x1000,
0x00410400:0x1000,
0x00410600:0x1000,
0x00410800:0x1000,
0x00411000:0x1000,
0x00412000:0x1000,
0x00413000:0x1000,
0x00414000:0x1000
The error is
ERROR (duplicate_node_names): Duplicate node name /memory@410
ERROR (duplicate_node_names): Duplicate node name /memory@410
ERROR (duplicate_node_names): Duplicate node name /memory@410
ERROR (duplicate_node_names): Duplicate node name /memory@410
ERROR (duplicate_node_names): Duplicate node name /memory@410
ERROR (duplicate_node_names): Duplicate node name /memory@410
ERROR: Input tree has errors, aborting (use -f to force output)
cause:
the merge_overlapping_memory_regions works not well in partial overlap case
change:
1. use forward way to avoid weird reverse iterator behavior in C++
2. use address but not page number since the base addresses are
all aligned in make_mems
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
For some reason, the old accessors for the non-sparse version were left
dangling. These methods are used by the --kernel and --initrd options,
and so those options were just broken.
This also fixes a memory leak and refactors the implementation a bit.
Parshintsev Anatoly
Jerry Zhao
Andrew Waterman
Tim Newsome
Jerin Joy
Weiwei Li
Rupert Swarbrick
Rupert Swarbrick
John Ingalls
Elmar Melcher
Chih-Min Chao
Zitao Fang