riscv-isa-sim

3 Tags

17 MiB

Branch: master

Author	SHA1	Message	Date
Dan Smathers	de8e0588ac	update set_msw/clear_msw/set_mtimer/clear_mtimer Added ifndef to clint addresses instead of hard-coding Added clear_msw and clear mtimer Tested against Sail/isa-sim with new proposed Smclint/Ssclint arch-tests https://github.com/riscv-non-isa/riscv-arch-test/pull/372 Building a baseline of interrupt tests that changes to SAIL/isa-sim can be tested against when other interrupt extensions are added. Signed-off-by: Dan Smathers <dan.smathers@seagate.com>	3 years ago
Neel Gala	95615360d2	clean up for rv32e_unratified.	4 years ago
Neel Gala	e78559f521	clean up the the arch-test directory to avoid copypasta - move all common stuff to a Makefile_common.inc - include this file in all individual Makefile.includes	4 years ago
Neel Gala	1b3a5b96f8	adding ports to run F, D and E extension architectural tests on spike	4 years ago
davidharrishmc	82c5d885d1	Update README.md (#797 ) Corrected path to Makefile.include	5 years ago
Allen Baum	6c18ef569c	replace old compliance name with new arch-test name in spike target README (#690 )	5 years ago
Neel Gala	60f7eda71d	fixed typos and paths for arch_test readme (#638 ) Co-authored-by: Neel Gala <neelgala@incoresemi.com>	5 years ago
Neel Gala	ccdbfacc9f	adding spike as a target to the arch-test-framework (#630 ) * files and collateral for adding spike as a target to the arch-test-framework * minor typo fix Co-authored-by: Neel Gala <neelgala@incoresemi.com>	5 years ago