riscv-isa-sim

Commit Graph

Author	SHA1	Message	Date
Andrew Waterman	3ab5756454	Merge pull request #2362 from jerryzj/fix/fli-c99-designator-warnings Use standard C++ initializers for fli_* constant tables	21 hours ago
Jerry Zhang Jian	0335d5480a	Use standard C++ initializers for fli_* constant tables C99 array designators ([index] = value) are not valid C++ and trigger -Wc99-designator under clang. C++20 designated initializers only cover named members, not array indices, so use sequential static constexpr tables and keep rs1 encodings in comments. Signed-off-by: Jerry Zhang Jian <jerry.zhangjian@sifive.com>	2 days ago
Andrew Waterman	3d8eb089bd	Merge pull request #2356 from sinhaparth5/fix/timing-before-trigger-step Debug/Trace: stop execution when a timing-before trigger matches	1 week ago
Andrew Waterman	adc12d2a3d	Merge pull request #2357 from riscv-software-src/fix-2347 Only check instruction-fetch data triggers on complete instructions	1 week ago
Andrew Waterman	168f52e056	Only check instruction-fetch data triggers on complete instructions Signed-off-by: Andrew Waterman <andrew@sifive.com>	1 week ago
Andrew Waterman	6f9038152e	Factor instruction-fetch logic out of refill_icache Also separate the case where the first fetch is a simple intrapage TLB hit, which will help with a subsequent change. Signed-off-by: Andrew Waterman <andrew@sifive.com>	1 week ago
Parth	38e57ba3ba	Debug/Trace: stop execution when a timing-before trigger matches End the current processor step after taking the trigger action, preventing an extra debug-ROM or trap-handler instruction from executing before the caller observes the matched instruction’s architectural context.	1 week ago
Andrew Waterman	cb71dabb92	Merge pull request #2354 from mslijepc/mslijepc_20260728_clint-size changed default clint size	1 week ago
mslijepc	491814140c	changed default clint size	1 week ago
Andrew Waterman	520a5f1850	Merge pull request #2353 from riscv-software-src/fix-zvbdota-asm Disassemble Zvbdota instructions' ci field correctly	2 weeks ago
Andrew Waterman	9cf2943fcb	Disassemble Zvbdota instructions' ci field correctly Signed-off-by: Andrew Waterman <andrew@sifive.com>	2 weeks ago
Andrew Waterman	1557427229	Merge pull request #2352 from riscv-software-src/fix-2350 Fix PNCLIPUP.W by avoiding signed arithmetic	2 weeks ago
Andrew Waterman	089ee9c789	Merge pull request #2297 from riscv-software-src/fix-2296 Report CBO.ZERO faults on effective address, not base address	2 weeks ago
Andrew Waterman	8c10cf690b	Merge pull request #2349 from binno/spmp_fix Delete useless error code	2 weeks ago
Andrew Waterman	8b5f2b2158	Remove redundant set_vxsat calls Signed-off-by: Andrew Waterman <andrew@sifive.com>	2 weeks ago
Andrew Waterman	cfa8d89635	Fix PNCLIPUP.W by avoiding signed arithmetic Signed-off-by: Andrew Waterman <andrew@sifive.com>	2 weeks ago
Binno	84a8cfc49b	Delete useless error code Signed-off-by: Binno <binno.shen@sifive.com>	2 weeks ago
Andrew Waterman	907862288f	Merge pull request #2345 from riscv-software-src/fix-2319 Fix pmulhsu.w.h0 shift amount	3 weeks ago
Andrew Waterman	d9cfec7aeb	Merge pull request #2343 from EccoTheDolphin/aap-sc/mmio_ok_gone get rid of mmio_ok checks	3 weeks ago
Andrew Waterman	3462556812	Fix pmulhsu.w.h0 shift amount Resolves #2319 cc @chihminchao Signed-off-by: Andrew Waterman <andrew@sifive.com>	3 weeks ago
Anatoly Parshintsev	c73d357a1a	get rid of mmio_ok checks before this patch, hart access to debug module region was controlled in two places: 1. pmp_ok performed the normal architectural PMP checks, but bypassed them for debug module region accesses while the hart was in debug mode. 2. mmio_ok rejected debug module region accesses from harts outside debug mode. Processor-less debug_mmu accesses remained allowed. This patch moves the control decision entirely to pmp_ok routine: allow debug module regoin accesses in debug mode and deny them otherwise. This check is run before the no-PMP fast path, making mmio_ok redundant. Additionally, we flush the TLB on processor reset because it may contain stale entries from the time while hart was in debug mode.	3 weeks ago
Andrew Waterman	b2d6fbf0fd	Merge pull request #2339 from riscv-software-src/fix-2334 Don't update any arch state on vl=0 dot products	4 weeks ago
Andrew Waterman	e9dfa38bb5	Don't update any arch state on vl=0 dot products Fixes #2334 Signed-off-by: Andrew Waterman <andrew@sifive.com>	4 weeks ago
Andrew Waterman	b0093c40c3	Merge pull request #2338 from riscv-software-src/rename-dot Fix names of dot-product instructions	4 weeks ago
Andrew Waterman	3e6a4ea28b	Disassemble dot instructions Signed-off-by: Andrew Waterman <andrew@sifive.com>	4 weeks ago
Andrew Waterman	bfe589c221	Fix names of dot-product instructions In accordance with https://github.com/riscv/riscv-isa-manual/pull/2618 Signed-off-by: Andrew Waterman <andrew@sifive.com>	4 weeks ago
Andrew Waterman	f7bd55744a	Merge pull request #2310 from chihminchao/fix-rvp Fix rvp	4 weeks ago
Chih-Min Chao	f35109939a	rvp: some rv32 multiplication instructions require extra sign-extension Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	1 month ago
Max Chou	5c1a3c40bf	rvp: Fix shift amount masking in PSLL.DWS Use 5-bit mask (0x1F) for shift amount instead of 8-bit field extraction. Spec defines rs2[4:0] as shift amount. Also removes incorrect >= 32 check that zeroed result. Fixed instruction: - PSLL.DWS: P-ext spec Changed: P_FIELD(RS2, 0, 8) with >= 32 check → RS2 & 0x1F Signed-off-by: Max Chou <max.chou@sifive.com>	2 months ago
Max Chou	85c84f0d27	rvp: Fix packed multiply-subtract operation logic Corrects swapped add/subtract operators in packed 2-way multiply loop. Spec requires (p0 - p1) but implementation computed (p1 - p0). Even elements should add, odd elements should subtract. Fixed instructions: - PM2WSUB.H: P-ext spec - PM2WSUBA.H: P-ext spec Changed: Swapped += and -= for (j & 1) conditional Signed-off-by: Max Chou <max.chou@sifive.com>	2 months ago
Max Chou	4796690c71	rvp: Fix multiply-accumulate result extraction shift amount Corrects shift amount for extracting bits [47:16] from 48-bit multiply-accumulate products. Implementation used 32-bit shift but spec requires 16-bit shift to extract high portion. Fixed instructions: - MHACC.H0: P-ext spec - MHACC.H1: P-ext spec - MHACCSU.H0: P-ext spec - MHACCSU.H1: P-ext spec Changed: mres >> 32 → mres >> 16 Signed-off-by: Max Chou <max.chou@sifive.com>	2 months ago
Chih-Min Chao	36c40b4853	rvp: add missing vxsat updating Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	2 months ago
Chih-Min Chao	6e0889925b	rvp: fix and simplify behavior Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	3 months ago
Chih-Min Chao	38886e3dc7	rvp: refine the sign-extension and extration of mulplication result Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	3 months ago
Chih-Min Chao	59b63cf58d	rvp: helper macro doesn't fit some nclip operation also refine writing path to RD Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	3 months ago
Chih-Min Chao	8b1ad63088	rvp: do sext32 before writing to rd for rv32 Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	3 months ago
Chih-Min Chao	72a5c14248	rvp: fix the result extraction of multiplication Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	3 months ago
Chih-Min Chao	4caf3468b9	rvp: fix shift w/ or w/o saturation Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	3 months ago
Chih-Min Chao	f720135842	rvp: handle rv64 and rv32 overlap again Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	3 months ago
Andrew Waterman	55b4658dbf	Merge pull request #2331 from binno/fix_naming_typo Fix name typo for zvqwbdota8i/zvqwbdota16i extension	1 month ago
Binno	fce96c0b14	Fix name typo for zvqwbdota8i/zvqwbdota16i extension Signed-off-by: Binno <binno.shen@sifive.com>	1 month ago
Andrew Waterman	de0425ad62	Merge pull request #2324 from binno/enable_deleg_bit Switch exception bits by correspond extensions	1 month ago
Andrew Waterman	cb645a0633	Merge pull request #2330 from mslijepc/mslijepc_20260625_ziccrse Add missing Ziccrse extension to disassembler fallback	1 month ago
mslijepc	971b62caa0	Add missing Ziccrse extension to disassembler fallback	1 month ago
Andrew Waterman	27731d158d	Merge pull request #2327 from mslijepc/mslijepc_20260624_ziccamoa Adding Ziccamoa extension to disassembler	1 month ago
mslijepc	f08229cc74	Add missing Ziccamoa extension to disassembler fallback	1 month ago
Andrew Waterman	33c1eb2b25	Merge pull request #2325 from binno/spmp_fixes Apply fixes for SPMP extension	1 month ago
Binno	02d6fc7b4c	Add smpmpdeleg keyword for smpmpdeleg extension Signed-off-by: Binno <binno.shen@sifive.com>	1 month ago
Andrew Waterman	040bdb4c0c	Merge pull request #2322 from EccoTheDolphin/aap-sc/pmp_debug_relaxation relax pmp checks for RWX accesses to debug ROM in debug mode	1 month ago
Anatoly Parshintsev	57af22a174	relax pmp checks for RWX accesses to debug ROM in debug mode Prior this patch it was impossible to enter debug mode when mseccfg.MML was set. The reason is that debug ROM requires both RW and X permissions for debug module to function properly (for example for progbuf execution). This patch relaxes pmp checks and allows unconditional access to debug firmware area whenever the processor is in debug state.	2 months ago

1 2 3 4 5 ...

4149 Commits (master) All Branches Search

4149 Commits (master)

All Branches