riscv-isa-sim

Commit Graph

Author	SHA1	Message	Date
Palmer Dabbelt	773fab34d4	spec bump	9 years ago
Andrew Waterman	ee80f2851a	PUM -> SUM; expose MXR to S-mode	9 years ago
Andrew Waterman	5ed1c1f9de	Simplify interrupt-stack discipline `f2ed45b179`	9 years ago
Andrew Waterman	17e3ef9618	Implement mstatus.TW, mstatus.TVM, and mstatus.TSR	9 years ago
Andrew Waterman	3c8dafeef0	Don't overload illegal instruction trap in interactive code	9 years ago
Andrew Waterman	cbaa72d24c	Sv57 and Sv64 are not spec'd yet	9 years ago
Andrew Waterman	6db0707687	New counter enable scheme https://github.com/riscv/riscv-isa-manual/issues/10	9 years ago
Tim Newsome	ab8a5631c3	Update bits to latest spec.	9 years ago
Tim Newsome	5a9e289624	Implement halt request. Also clean up some vestigial code.	9 years ago
Tim Newsome	21fb735d62	Improve debug performance. It's still pitiful, but less so. (5KB/s download speed.) The tweaks involve switching to the other context as soon as it might be helpful. The two contexts are executing code, and handling JTAG TAP input.	9 years ago
Tim Newsome	0e848d2f43	Don't waste time spinning in place in debug mode	9 years ago
Andrew Waterman	13639b9c45	serialize simulator on wfi This improves simulator perf when a thread is idle, or waiting on HTIF.	9 years ago
Andrew Waterman	b47e8c0a19	Take M-mode interrupts over S-mode interrupts	9 years ago
Andrew Waterman	f478eef851	permit MMIO loads to MSIP bit	9 years ago
Andrew Waterman	67cd71d9ec	Make HW setting of PTE A/D bits optional (by configure arg) https://github.com/riscv/riscv-isa-manual/issues/14	9 years ago
Andrew Waterman	eace559960	Spike uarch needs TLB flush after SPTBR write	9 years ago
Tim Newsome	e36bacd9bc	Compress log output of jump-to-self loops. This helps hugely when reading "spike -l" output when debugging is going on.	9 years ago
Tim Newsome	8c19757cf5	Remove noisy debugs. This version was able to download code, and run to a breakpoint.	9 years ago
Tim Newsome	8dd673b744	Set cmderr when data is accessed while busy.	9 years ago
Tim Newsome	f88504000a	Implement autoexec. DMI op 2 is just write now. Now passing MemTest{8,16,32,64}	9 years ago
Tim Newsome	4df7f6d279	Implement resume (untested).	9 years ago
Andrew Waterman	d503765577	sfence.vm -> sfence.vma	9 years ago
Tim Newsome	294a0572c4	Implement program buffer preexec/postexec. I only tested preexec.	9 years ago
Tim Newsome	ae67cde583	dbus -> dmi	9 years ago
Tim Newsome	1a62370146	Abstract register read mostly working. Fails with not supported for 128-bit. Fails with exception (on rv32) with 64-bit. Succeeds (on rv32) with 32-bit.	9 years ago
Tim Newsome	f7f1105040	Fix stack overflow and support --rbb-port=0	9 years ago
Tim Newsome	b4de20a92e	Entering debug mode now jumps to "dynamic rom"	9 years ago
Tim Newsome	8a09a059dc	Implement hartstatus field.	9 years ago
Tim Newsome	a62a819679	Remove gdbserver support. Maybe some day we can bring it back, implementing direct access into registers and memory so it would be fast. That would be the way to usefully debug code running in spike, as opposed to the way that mirrors the actual debug design as it might be implemented in hardware.	9 years ago
Tim Newsome	c704a804ba	Add writable ibuf and data registers.	9 years ago
Tim Newsome	4845819872	Serve up a correct dmcontrol register.	9 years ago
Andrew Waterman	a30f158300	Encode VM type in sptbr, not mstatus https://github.com/riscv/riscv-isa-manual/issues/4 Also, refactor gdbserver code to not duplicate VM decoding logic.	9 years ago
Tim Newsome	94277648d5	OpenOCD does a dmi read and gets dummy value back.	9 years ago
Tim Newsome	daaf28f729	Merge pull request #83 from bacam/gdb-protocol-fixes Gdb protocol fixes	9 years ago
Tim Newsome	1f65ba49ea	Remove unnecessary circular buffer code.	9 years ago
Tim Newsome	4695be7cea	Refactor remote bitbang code.	9 years ago
Tim Newsome	9be1570420	OpenOCD RISC-V code now gets to scan out dtmcontrol.	9 years ago
Tim Newsome	f6a7fe2c4e	OpenOCD can now scan out the hacked IDCODE.	9 years ago
Tim Newsome	d1f2cf337e	OpenOCD connects, and sends some data that we receive.	9 years ago
Andrew Waterman	9e012462f5	Fix interrupt delegation for coprocessors	9 years ago
Andrew Waterman	6642f8c745	For FMIN(sNaN, x) and FMIN(qNaN, qNaN), return canonical NaN Resolves #76	9 years ago
Andrew Waterman	d392463e5c	Set xPIE=1 on xRET Resolves #88.	9 years ago
Andrew Waterman	e9e30598e0	Only allow SIP.SSIP to be toggled if the interrupt is delegated	9 years ago
Andrew Waterman	b387326dbc	Make SIP.STIP read-only h/t Ron Minnich See https://groups.google.com/a/groups.riscv.org/forum/#!topic/isa-dev/JV-Hj3W5Kw8	9 years ago
David Craven	51a0e1e965	Comply with GNU coding standards. Currently the DESTDIR variable is not used correctly which leads to bogus RUNPATH entries. https://www.gnu.org/prep/standards/html_node/DESTDIR.html	9 years ago
Brian Campbell	f38dcde0d8	Only read exception flag in gdb register read/write. (#85 ) The flag is 32 bits, and if we read 64/128 bits then we get fragments of S1 too and can accidentally send an error. Fixes #84.	9 years ago
Brian Campbell	7647707a60	Fix gdb communication error (#82 )	9 years ago
Brian Campbell	71f64bfe4e	Remove extra gdb protocol responses on register writes	9 years ago
Brian Campbell	9e3b7bdc5a	Fix gdb protocol register read of S0	9 years ago
Stefan O'Rear	07ff3f3b0b	Use correct format codes for reg_t and size_t Fixes 32-bit build.	9 years ago

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943 Commits (debug_rom) All Branches Search

943 Commits (debug_rom)

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