riscv-isa-sim

Commit Graph

Author	SHA1	Message	Date
Tim Newsome	9a2904a97a	Clean up/optimize Debug ROM. It's 3 instructions shorter now.	8 years ago
Tim Newsome	f9d2be538b	Implement halt groups (#280 ) * Update debug_defines from latest spec. * Implement halt groups. This lets the debugger halt multiple harts near simultaneously. * Revert encoding, which I updated accidentally.	7 years ago
Andrew Waterman	5b08bf5c3c	Further fix PMP checks for partially-matching accesses (#270 ) `ee6fe6501a` didn't get this right, as it failed to add the offset to the address when checking each 4-byte sector of the access against hte PMPs.	7 years ago
Tim Newsome	da8ab7d18d	Fix small bug in debug example. (#277 ) 23 is the wrong line number. Avoid future problems by using a label.	7 years ago
Luís Marques	1916b185e2	Fix use of old name `riscv-isa-run` (#269 )	7 years ago
Andrew Waterman	2b38c82833	Merge pull request #274 from hakrdinesh/master openbsd port of spike and its build documentation	7 years ago
Dinesh Thirumurthy	97ed2cc42a	need to install dtc pkg on openbsd	7 years ago
Dinesh Thirumurthy	c661d9c428	doc typo fix on README.md, sorry.	7 years ago
Dinesh Thirumurthy	5e6973db21	build instructions for openbsd	7 years ago
Dinesh Thirumurthy	ec694bbdda	fixing compilation errors on openbsd	7 years ago
Dinesh Thirumurthy	5907e70c43	bash can be at /usr/local/bin, on openbsd	7 years ago
Andrew Waterman	ee6fe6501a	Fix PMP checks for partially-matching accesses (#270 ) PMP checks should unconditionally fail if the PMP matches part of, but not all of, an access. We got this right, but went too far: we checked whether _any_ PMP matches in this manner. In fact, only the first PMP that maches any of the bytes should be checked in this manner.	7 years ago
Tim Newsome	c544846020	Merge pull request #265 from riscv/debug_test Add --dmi-rti and --abstract-rti to test OpenOCD.	7 years ago
Andrew Waterman	06bafbf547	Reserve the PMP R=0 W=1 combination This was a post-v1.10 amendment to the privileged spec. `059f64c941`	7 years ago
Andrew Waterman	c20d84c6f3	Flush I/O buffers before forking This prevents duplicate I/Os to buffered streams early in the program.	7 years ago
Tim Newsome	5c18497225	Add --dmi-rti and --abstract-rti to test OpenOCD. Optionally make spike behave more like real hardware, to automatically test OpenOCD's handling of such hardware.	7 years ago
Tim Newsome	ba04fcfd1c	Correct address autoincrement calls. (#263 ) Now we do what the spec says we should do. This ended up not having any effect on the current way OpenOCD performs system bus accesses.	7 years ago
naufal	65c8ac48af	commands render correctly in README.md now, included in code block	7 years ago
Andrew Waterman	0125268690	Report misaligned-address exception on failed store-conditionals Previously, the exception would only be raised if the store-conditional would have succeeded.	8 years ago
Palmer Dabbelt	120d2975b3	Merge pull request #247 from heshamelmatary/noisy_until Provide a noisy until interactive command	8 years ago
Hesham Almatary	dc6871efef	Provide a noisy until interactive command This is useful for example when the trace until a PC value needs to be extracted (#246)	8 years ago
Andrew Waterman	f54ff67b56	Set marchid to assigned value 5 https://github.com/riscv/riscv-isa-manual/blob/master/marchid.md TODO: allow Spike users to override marchid/mvendorid/mimpid to mimic their hardware implementations more closely.	8 years ago
Andrew Waterman	1d66556fca	fix disassembly of c.addi4spn Resolves #243	8 years ago
Andrew Waterman	8478969176	Add comment about CSR read side effects	8 years ago
Andrew Waterman	6063149556	For backwards compatibility, reset PMP to permit all accesses	8 years ago
Andrew Waterman	55ef17645d	Add PMP support	8 years ago
takeoverjp	0b8700bb61	Add "--log-cache-miss" option to generate a log of cache miss. (#241 ) * Add "--log-cache-miss" option to generate a log of cache miss. - This option must be used with "--ic" and/or "--dc" options to enable cache simulation. - This option is useful with "-l" option to understand which instruction has caused the cache miss. * Modify log format of cache miss to reduce log size.	8 years ago
Andrew Waterman	6fecdb16d7	Update README	8 years ago
Tim Newsome	def4c5b104	Merge pull request #235 from riscv/sba Fix cut-and-paste bug in 64-bit SBA loads.	8 years ago
Tim Newsome	7de234911f	Fix cut-and-paste bug in 64-bit SBA loads. Fixes #234.	8 years ago
Andrew Waterman	aff796dbf6	Handle spike-dasm inputs with leading 0x correctly	8 years ago
Tim Newsome	176ff23c6f	Add dummy custom debug registers, to test OpenOCD. (#233 )	8 years ago
Andrew Waterman	fad88d8140	Fix several disassembler bugs h/t Shane Lardinois	8 years ago
Andrew Waterman	747a54b103	Add --disable-dtb option to suppress writing the DTB to memory	8 years ago
Andrew Waterman	60235e3816	Make IRQ_COP read-only/undelegable unless coprocessor is present	8 years ago
Andrew Waterman	b6ec196e9e	Instantiate disassembler after max_xlen is known This fixes RVC disassembly. It's done in a way that doesn't break `2cd60b277e`	8 years ago
Andrew Waterman	8a485de092	Don't increment instret immediately after it is written (#231 ) This brings Spike into compliance with this clause in the spec: https://github.com/riscv/riscv-isa-manual/blob/master/src/csr.tex#L96	8 years ago
Tim Newsome	bed0a54fda	Fix 2 trigger corner cases. (#229 ) 1. When hitting a trigger during a single step, dcsr.cause must reflect the trigger not the step. 2. Also check for triggers on accesses that require a slow path fetch.	8 years ago
Andrew Waterman	1ff2a70ec8	Make sstatus.MXR readable h/t @taoliug	8 years ago
SeungRyeol Lee	2cd60b277e	Fix using the uninitialized disassemble object. (#220 ) This fixes runtime crash when custom extension registers its disassembly.	8 years ago
Andrew Waterman	95487c248a	Refactor and fix LR/SC implementation (#217 ) - Use physical addresses to avoid homonym ambiguity (closes #215) - Yield reservation on store-conditional (`03a5e722fc`) - Don't yield reservation on exceptions (it's no longer required).	8 years ago
Tim Newsome	cc50a327a5	Merge pull request #212 from riscv/hartsel Update debug_defines.h	8 years ago
Tim Newsome	5542d31fcf	Update debug_defines.h Add support for hartselhi parsing, but other parts of the debug code still don't support more than 1024 harts.	8 years ago
Andy Wright	d6fcfdebf6	Put simif_t declaration in its own file. (#209 ) By separating the simif_t declaration from the sim_t declaration, the simif_t declaration no longer depends on fesvr header files. This simplifies compilation of custom sim class implementations that don't depend on fesvr.	8 years ago
Prashanth Mundkur	19efe7d112	Fix install of missed header. (#207 )	8 years ago
Prashanth Mundkur	545911797f	Extract out device-tree generation and compilation into an exported api. (#197 )	8 years ago
Andrew Waterman	d48f107dba	Revert "C.LWSP and C.LDSP with rd=0 are legal instructions" See `01190b6ebe`	8 years ago
Andrew Waterman	d336aee08b	C.LWSP and C.LDSP with rd=0 are legal instructions This mistake derives from an ambiguity in the specification that has since been corrected: `272d038abe`	8 years ago
Andrew Waterman	d2e9a109e8	Fix commit log for serializing instructions Resolves #199	8 years ago
Andrew Waterman	3d016e2765	Only break out of the simulator loop on WFI, not on CSR writes Breaking out of the loop on WFI was intended to let other threads run when the current thread has no work to do. There's no advantage to doing so on CSR writes, and the unintentional change in thread interleaving broke some test programs that relied on short timer periods.	8 years ago

1 2 3 4 5 ...

943 Commits (debug_rom) All Branches Search

943 Commits (debug_rom)

All Branches