46f2fb1d9e
[sim] hacked in a dcache simulator
15 years ago
913ee989dd
[xcc,sim,opcodes] added c.addiw
16 years ago
d5518cd4d9
[xcc,sim,opcodes] added more RVC instructions
16 years ago
c0cd05e70b
[sim] fixed divw/remw crashing simulator
16 years ago
c6b549289a
[xcc,sim] rv64 'w' instruction semantics changed
they no longer require their inputs to be canonicalized 32b values, so
this speeds up mixed int/long code sequences.
16 years ago
0433532951
[xcc,sim,opcodes] added rvc conditional branches
16 years ago
95d58037b2
[sim] removed undefined behavior for non-canonical inputs
16 years ago
6e2844c1b5
[sim] added "str" debug command
it prints the c string starting at the specified memory address.
16 years ago
5c96429584
[sim] fixed jalr immediate bug
16 years ago
481c9e8fd8
[sim] added icache simulator (disabled by default)
16 years ago
402b4e8600
[xcc,pk,sim] added privileged cflush instruction
16 years ago
f5f9ed0a0d
[xcc,sim] fixed RM field
16 years ago
5fe6c52270
[xcc,sim] rvc loads and stores
16 years ago
06062a1b5c
[sim,pk] fixed minor pk bugs and trap codes
16 years ago
2032e6c6b7
[sim] fixed FSR exception field bug
16 years ago
66eda0b75e
[xcc,sim,opcodes] more rvc instructions and bug fixes
16 years ago
4b534147c0
[sim] add disable option for vector
16 years ago
7198e5091f
[sim] set SR_EV for uts
16 years ago
68f504c52e
[sim] add vector traps to vector instructions
16 years ago
e9567ce7bb
[sim] add vt stuff
16 years ago
c8de0ef0fa
[xcc, sim] added rvc insn c.li; misc fixes
16 years ago
3c6275887f
[sim,pk] reorganized status register
16 years ago
d31b94409c
[xcc,pk,sim,opcodes] added first RVC instruction
16 years ago
98598ca5e2
[sim] fixed multiply-high in rv32
16 years ago
dde934bb5b
[pk,sim] fixed parse-opcodes bug
was causing spurious illegal instruction traps
16 years ago
02166b2691
[opcodes,pk,sim,xcc] fix utidx - add rd
16 years ago
a174f4bfdb
[opcodes,pk,sim,xcc] fix vector mem instruction format, add vector seg mem instructions
16 years ago
fed0e53ae7
[opcodes,pk,sim,xcc] add leftover vector instructions (vf, etc.)
16 years ago
9e58791c6b
[opcodes,pk,sim,xcc] add vector mem instructions
16 years ago
c17b57db55
[opcodes,pk,sim,xcc] add stop,utidx instructions
16 years ago
aab3bc1244
[opcodes,pk,sim,xcc] add fence instructions for vector unit
16 years ago
eb6cb4b2ee
[xcc] fixed bug in amo{maxu,minu}.w
16 years ago
99d358e589
[opcodes] minor opcode changes
16 years ago
1598e2964e
[sim,pk,xcc,opcodes] removed fminmag/fmaxmag
16 years ago
3fb2ead615
[xcc,pk,opcodes,sim] updated encoding/insn names
16 years ago
d17ab96ab5
[sim] LWU now illegal in RV32
16 years ago
68591c3c45
[xcc,sim] branches are pc-relative (not pc+4) again
16 years ago
2c3ff5536d
[xcc,opcodes,pk,sim] krste's re-renaming spree
16 years ago
f37be621fe
[xcc,sim,opcodes] removed mtflh/mffl/mffh
in rv32 these will be replaced with loads and stores.
16 years ago
75d9ab427d
[sim,pk] added interrupt-pending field to cause reg
16 years ago
c983d273b2
[sim,xcc,opcodes] added back mtflh.d
16 years ago
28a6b2a350
[opcodes,pk,sim,xcc] synci now bombs whole icache
16 years ago
94dc73b7f1
[xcc,opcodes,pk,sim] cleanup to FP ISA
- Added 5th rounding mode
- Removed MFCR/MTCR in favor of MFFSR/MTFSR (it was the only CR...)
- merged MTF.D with MTFLH.D; operation depends on RV32/RV64 mode
- made MFFL.D and MFFH.D illegal in RV64
16 years ago
ada2fe414b
[sim] added nearest/ties to max magnitude rounding mode
16 years ago
dc1aa62411
[sim] changed divide-by-0 semantics
now it always gives -1, no matter the signedness.
16 years ago
76ee8711f8
[sim,opcodes] add mulhsu instruction
16 years ago
5bae2bf372
[opcodes,pk,sim,xcc] great renumbering of 2011, part deux
16 years ago
f0063c2e8b
[sim, pk, xcc, opcodes] great instruction renaming of 2011
16 years ago
21ce327f5d
[opcodes, sim, xcc] made *w insns illegal in RV32
now generic variants behave differently in RV32 and RV64.
16 years ago
5ddec097b8
[opcodes, pk, sim, xcc] removed nor, normalized macros to addi
16 years ago
Andrew Waterman
Andrew Waterman
Yunsup Lee