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rvv: rename vfncvt suffix and add rod rouding type 

1. vfncvt*.v  -> vfncvt*.w
  2. add vfncvt.rod.f.f.w

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
pull/366/head
Chih-Min Chao 7 years ago
parent
08343bba3b
commit
fd132e6214
9 changed files with 55 additions and 41 deletions
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  1. 36
      riscv/encoding.h
  2. 2
      riscv/insns/vfncvt_f_f_w.h
  3. 2
      riscv/insns/vfncvt_f_x_w.h
  4. 2
      riscv/insns/vfncvt_f_xu_w.h
  5. 7
      riscv/insns/vfncvt_rod_f_f_w.h
  6. 0
      riscv/insns/vfncvt_x_f_w.h
  7. 0
      riscv/insns/vfncvt_xu_f_w.h
  8. 11
      riscv/riscv.mk.in
  9. 36
      spike_main/disasm.cc

36
riscv/encoding.h
View File

@ -1002,18 +1002,18 @@
#define MASK_VFWCVT_F_X_V 0xfc0ff07f
#define MATCH_VFWCVT_F_F_V 0x88061057
#define MASK_VFWCVT_F_F_V 0xfc0ff07f
#define MATCH_VFNCVT_XU_F_V 0x88081057
#define MASK_VFNCVT_XU_F_V 0xfc0ff07f
#define MATCH_VFNCVT_X_F_V 0x88089057
#define MASK_VFNCVT_X_F_V 0xfc0ff07f
#define MATCH_VFNCVT_F_XU_V 0x88091057
#define MASK_VFNCVT_F_XU_V 0xfc0ff07f
#define MATCH_VFNCVT_F_X_V 0x88099057
#define MASK_VFNCVT_F_X_V 0xfc0ff07f
#define MATCH_VFNCVT_F_F_V 0x880a1057
#define MASK_VFNCVT_F_F_V 0xfc0ff07f
#define MATCH_VFNCVT_ROD_F_F_V 0x880a9057
#define MASK_VFNCVT_ROD_F_F_V 0xfc0ff07f
#define MATCH_VFNCVT_XU_F_W 0x88081057
#define MASK_VFNCVT_XU_F_W 0xfc0ff07f
#define MATCH_VFNCVT_X_F_W 0x88089057
#define MASK_VFNCVT_X_F_W 0xfc0ff07f
#define MATCH_VFNCVT_F_XU_W 0x88091057
#define MASK_VFNCVT_F_XU_W 0xfc0ff07f
#define MATCH_VFNCVT_F_X_W 0x88099057
#define MASK_VFNCVT_F_X_W 0xfc0ff07f
#define MATCH_VFNCVT_F_F_W 0x880a1057
#define MASK_VFNCVT_F_F_W 0xfc0ff07f
#define MATCH_VFNCVT_ROD_F_F_W 0x880a9057
#define MASK_VFNCVT_ROD_F_F_W 0xfc0ff07f
#define MATCH_VFSQRT_V 0x8c001057
#define MASK_VFSQRT_V 0xfc0ff07f
#define MATCH_VFCLASS_V 0x8c081057
@ -2168,12 +2168,12 @@ DECLARE_INSN(vfwcvt_x_f_v, MATCH_VFWCVT_X_F_V, MASK_VFWCVT_X_F_V)
DECLARE_INSN(vfwcvt_f_xu_v, MATCH_VFWCVT_F_XU_V, MASK_VFWCVT_F_XU_V)
DECLARE_INSN(vfwcvt_f_x_v, MATCH_VFWCVT_F_X_V, MASK_VFWCVT_F_X_V)
DECLARE_INSN(vfwcvt_f_f_v, MATCH_VFWCVT_F_F_V, MASK_VFWCVT_F_F_V)
DECLARE_INSN(vfncvt_xu_f_v, MATCH_VFNCVT_XU_F_V, MASK_VFNCVT_XU_F_V)
DECLARE_INSN(vfncvt_x_f_v, MATCH_VFNCVT_X_F_V, MASK_VFNCVT_X_F_V)
DECLARE_INSN(vfncvt_f_xu_v, MATCH_VFNCVT_F_XU_V, MASK_VFNCVT_F_XU_V)
DECLARE_INSN(vfncvt_f_x_v, MATCH_VFNCVT_F_X_V, MASK_VFNCVT_F_X_V)
DECLARE_INSN(vfncvt_f_f_v, MATCH_VFNCVT_F_F_V, MASK_VFNCVT_F_F_V)
DECLARE_INSN(vfncvt_rod_f_f_v, MATCH_VFNCVT_ROD_F_F_V, MASK_VFNCVT_ROD_F_F_V)
DECLARE_INSN(vfncvt_xu_f_w, MATCH_VFNCVT_XU_F_W, MASK_VFNCVT_XU_F_W)
DECLARE_INSN(vfncvt_x_f_w, MATCH_VFNCVT_X_F_W, MASK_VFNCVT_X_F_W)
DECLARE_INSN(vfncvt_f_xu_w, MATCH_VFNCVT_F_XU_W, MASK_VFNCVT_F_XU_W)
DECLARE_INSN(vfncvt_f_x_w, MATCH_VFNCVT_F_X_W, MASK_VFNCVT_F_X_W)
DECLARE_INSN(vfncvt_f_f_w, MATCH_VFNCVT_F_F_W, MASK_VFNCVT_F_F_W)
DECLARE_INSN(vfncvt_rod_f_f_w, MATCH_VFNCVT_ROD_F_F_W, MASK_VFNCVT_ROD_F_F_W)
DECLARE_INSN(vfsqrt_v, MATCH_VFSQRT_V, MASK_VFSQRT_V)
DECLARE_INSN(vfclass_v, MATCH_VFCLASS_V, MASK_VFCLASS_V)
DECLARE_INSN(vfwadd_vv, MATCH_VFWADD_VV, MASK_VFWADD_VV)

2
riscv/insns/vfncvt_f_f_v.h → riscv/insns/vfncvt_f_f_w.h
View File

@ -1,6 +1,6 @@
// vfncvt.f.f.v vd, vs2, vm
VI_VFP_LOOP_BASE
VI_CHECK_SD;
VI_VFP_LOOP_BASE
auto vs2 = P.VU.elt<float64_t>(rs2_num, i);
P.VU.elt<float32_t>(rd_num, i) = f64_to_f32(vs2);
VI_VFP_LOOP_END

2
riscv/insns/vfncvt_f_x_v.h → riscv/insns/vfncvt_f_x_w.h
View File

@ -1,6 +1,6 @@
// vfncvt.f.x.v vd, vs2, vm
VI_VFP_LOOP_BASE
VI_CHECK_SD;
VI_VFP_LOOP_BASE
auto vs2 = P.VU.elt<int64_t>(rs2_num, i);
P.VU.elt<float32_t>(rd_num, i) = i64_to_f32(vs2);
VI_VFP_LOOP_END

2
riscv/insns/vfncvt_f_xu_v.h → riscv/insns/vfncvt_f_xu_w.h
View File

@ -1,6 +1,6 @@
// vfncvt.f.xu.v vd, vs2, vm
VI_VFP_LOOP_BASE
VI_CHECK_SD;
VI_VFP_LOOP_BASE
auto vs2 = P.VU.elt<uint64_t>(rs2_num, i);
P.VU.elt<float32_t>(rd_num, i) = ui64_to_f32(vs2);
VI_VFP_LOOP_END

7
riscv/insns/vfncvt_rod_f_f_w.h
View File

@ -0,0 +1,7 @@
// vfncvt.f.f.v vd, vs2, vm
VI_CHECK_SD;
VI_VFP_LOOP_BASE
softfloat_roundingMode = softfloat_round_odd;
auto vs2 = P.VU.elt<float64_t>(rs2_num, i);
P.VU.elt<float32_t>(rd_num, i) = f64_to_f32(vs2);
VI_VFP_LOOP_END

0
riscv/insns/vfncvt_x_f_v.h → riscv/insns/vfncvt_x_f_w.h
View File

0
riscv/insns/vfncvt_xu_f_v.h → riscv/insns/vfncvt_xu_f_w.h
View File

11
riscv/riscv.mk.in
View File

@ -526,11 +526,12 @@ riscv_insn_ext_v_alu_fp = \
vfmv_f_s \
vfmv_s_f \
vfmv_v_f \
vfncvt_f_f_v \
vfncvt_f_x_v \
vfncvt_f_xu_v \
vfncvt_x_f_v \
vfncvt_xu_f_v \
vfncvt_f_f_w \
vfncvt_f_x_w \
vfncvt_f_xu_w \
vfncvt_rod_f_f_w \
vfncvt_x_f_w \
vfncvt_xu_f_w \
vfnmacc_vf \
vfnmacc_vv \
vfnmadd_vf \

36
spike_main/disasm.cc
View File

@ -1029,15 +1029,23 @@ disassembler_t::disassembler_t(int xlen)
add_insn(new disasm_insn_t(#name ".vf", match_##name##_vf, mask_##name##_vf, \
{&vd, &vs2, &frs1, &opt, &vm})); \
#define DISASM_VFUNARY0_INSN(name, extra) \
add_insn(new disasm_insn_t(#name "cvt.xu.f.v", match_##name##cvt_xu_f_v, \
mask_##name##cvt_xu_f_v, {&vd, &vs2, &opt, &vm})); \
add_insn(new disasm_insn_t(#name "cvt.x.f.v", match_##name##cvt_x_f_v, \
mask_##name##cvt_x_f_v, {&vd, &vs2, &opt, &vm})); \
add_insn(new disasm_insn_t(#name "cvt.f.xu.v", match_##name##cvt_f_xu_v, \
mask_##name##cvt_f_xu_v, {&vd, &vs2, &opt, &vm})); \
add_insn(new disasm_insn_t(#name "cvt.f.x.v", match_##name##cvt_f_x_v, \
mask_##name##cvt_f_x_v, {&vd, &vs2, &opt, &vm}));
#define DISASM_VFUNARY0_INSN(name, extra, suf) \
add_insn(new disasm_insn_t(#name "cvt.xu.f." #suf, \
match_##name##cvt_xu_f_##suf, mask_##name##cvt_xu_f_##suf, \
{&vd, &vs2, &opt, &vm})); \
add_insn(new disasm_insn_t(#name "cvt.x.f." #suf, \
match_##name##cvt_xu_f_##suf, mask_##name##cvt_xu_f_##suf, \
{&vd, &vs2, &opt, &vm})); \
add_insn(new disasm_insn_t(#name "cvt.f.xu." #suf, \
match_##name##cvt_xu_f_##suf, mask_##name##cvt_xu_f_##suf, \
{&vd, &vs2, &opt, &vm})); \
add_insn(new disasm_insn_t(#name "cvt.f.x." #suf, \
match_##name##cvt_xu_f_##suf, mask_##name##cvt_xu_f_##suf, \
{&vd, &vs2, &opt, &vm})); \
if (extra) \
add_insn(new disasm_insn_t(#name "cvt.f.f." #suf, \
match_##name##cvt_xu_f_##suf, mask_##name##cvt_xu_f_##suf, \
{&vd, &vs2, &opt, &vm})); \
//OPFVV/OPFVF
//0b01_0000
@ -1070,14 +1078,12 @@ disassembler_t::disassembler_t(int xlen)
DISASM_OPIV__F_INSN(vfrdiv);
//vfunary0
DISASM_VFUNARY0_INSN(vf, 0);
DISASM_VFUNARY0_INSN(vf, 0, v);
DISASM_VFUNARY0_INSN(vfw, 1);
DISASM_INSN("vfwcvt.f.f.v", vfwcvt_f_f_v, 0, {&vd, &vs2, &opt, &vm});
DISASM_VFUNARY0_INSN(vfw, 1, v);
DISASM_VFUNARY0_INSN(vfn, 1);
DISASM_INSN("vfncvt.f.f.v", vfncvt_f_f_v, 0, {&vd, &vs2, &opt, &vm});
DISASM_INSN("vfncvt.rod.f.f.v", vfncvt_rod_f_f_v, 0, {&vd, &vs2, &opt, &vm});
DISASM_VFUNARY0_INSN(vfn, 1, w);
DISASM_INSN("vfncvt.rod.f.f.w", vfncvt_rod_f_f_w, 0, {&vd, &vs2, &opt, &vm});
//vfunary1
DISASM_INSN("vfsqrt.v", vfsqrt_v, 0, {&vd, &vs2, &opt, &vm});

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