From fbb46455d99771b7d3a2e60edc39acfd9d407f12 Mon Sep 17 00:00:00 2001
From: Scott Johnson <scott.johnson@arilinc.com>
Date: Mon, 1 Mar 2021 14:58:58 -0800
Subject: [PATCH] Correct RV64 vsstatus.UXL field (#659)

It was reading as 0, which is not a legal value.

In mstatus, UXL gets initialized by the call to set_csr(CSR_MSTATUS)
here in processor_t::reset().
---
 riscv/processor.cc | 1 +
 1 file changed, 1 insertion(+)

diff --git a/riscv/processor.cc b/riscv/processor.cc
index 07e6c627..c72e36b5 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -460,6 +460,7 @@ void processor_t::reset()
   state.dcsr.halt = halt_on_reset;
   halt_on_reset = false;
   set_csr(CSR_MSTATUS, state.mstatus);
+  state.vsstatus = state.mstatus & SSTATUS_VS_MASK;  // set UXL
   VU.reset();
 
   if (n_pmp > 0) {