rvv: extenc VU structure to support 0.9 new fields

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

riscv/execute.cc

@@ -107,7 +107,11 @@ static void commit_log_print_insn(processor_t *p, reg_t pc, insn_t insn)
     }
 
     if (!show_vec && (is_vreg || is_vec)) {
-        fprintf(log_file, " e%ld m%ld l%ld", p->VU.vsew, p->VU.vlmul, p->VU.vl);
+        fprintf(log_file, " e%ld %s%ld l%ld",
+                p->VU.vsew,
+                p->VU.vflmul < 0 ? "mf" : "m",
+                p->VU.vflmul < 0 ? (1 / p->VU.vflmul) : p->VU.vflmul,
+                p->VU.vl);
         show_vec = true;
     }
 

riscv/processor.cc

@@ -355,16 +355,27 @@ void processor_t::vectorUnit_t::reset(){
 }
 
 reg_t processor_t::vectorUnit_t::set_vl(int rd, int rs1, reg_t reqVL, reg_t newType){
+  int new_vlmul = 0;
   if (vtype != newType){
     vtype = newType;
     vsew = 1 << (BITS(newType, 4, 2) + 3);
-    vlmul = 1 << BITS(newType, 1, 0);
-    vediv = 1 << BITS(newType, 6, 5);
-    vlmax = VLEN/vsew * vlmul;
-    vmlen = vsew / vlmul;
-    reg_mask = (NVPR-1) & ~(vlmul-1);
+    new_vlmul = (BITS(newType, 5, 5) << 2) | BITS(newType, 1, 0);
+    new_vlmul = (int8_t)(new_vlmul << 5) >> 5;
+    vflmul = new_vlmul >= 0 ? 1 << new_vlmul : 1.0 / (1 << -new_vlmul);
+    vlmul = vflmul < 1 ? 1 : vflmul;
+    vlmax = (VLEN/vsew) * vflmul;
+    vemul = vflmul;
+    veew = vsew;
+    vta = BITS(newType, 6, 6);
+    vma = BITS(newType, 7, 7);
+    vediv = 1 << BITS(newType, 9, 8);
+
+    vill = !(vflmul >= 0.125 && vflmul <= 8)
+           || vsew > ELEN
+           || vflmul < ((float)vsew / ELEN)
+           || vediv != 1
+           || (newType >> 8) != 0;
 
-    vill = vsew > ELEN || vediv != 1 || (newType >> 7) != 0;
     if (vill) {
       vlmax = 0;
       vtype = UINT64_MAX << (p->get_xlen() - 1);

riscv/processor.h

@@ -453,9 +453,14 @@ public:
       void *reg_file;
       char reg_referenced[NVPR];
       int setvl_count;
-      reg_t reg_mask, vlmax, vmlen;
+      reg_t vlmax;
       reg_t vstart, vxrm, vxsat, vl, vtype, vlenb;
+      reg_t vma, vta;
       reg_t vediv, vsew, vlmul;
+      reg_t veew;
+      float vemul;
+      float vflmul;
+      reg_t vmel;
       reg_t ELEN, VLEN, SLEN;
       bool vill;
 

spike_main/disasm.cc

@@ -1,6 +1,7 @@
 // See LICENSE for license details.
 
 #include "disasm.h"
+#include <cassert>
 #include <string>
 #include <vector>
 #include <cstdarg>
@@ -319,9 +320,29 @@ struct : public arg_t {
     std::stringstream s;
     int sew = insn.v_sew();
     int lmul = insn.v_lmul();
+    auto vta = insn.v_vta() == 1 ? "ta" : "tu";
+    auto vma = insn.v_vma() == 1 ? "ma" : "mu";
     s << "e" << sew;
-    if (lmul != 1)
-      s << ",m" << lmul;
+    if(insn.v_frac_lmul()) {
+      std::string lmul_str = "";
+      switch(lmul){
+        case 3:
+          lmul_str = "f2";
+          break;
+        case 2:
+          lmul_str = "f4";
+          break;
+        case 1:
+          lmul_str = "f8";
+          break;
+        default:
+          assert(true && "unsupport fractional LMUL");
+      }
+      s << ", m" << lmul_str;
+    } else {
+      s << ", m" << (1 << lmul);
+    }
+    s << ", " << vta << ", " << vma;
     return s.str();
   }
 } v_vtype;