Add pre_v to processor state

This adds the prev_v field to track the previous virtual mode state. We
also assign it unconditionally to handle cases for trigger matching
like the following (pointed out by Scott Johnson):

    1) SRET from HS to VU: prev_v is set to 0
    2) Trap from VU to VS: state.v/prev_v won't be assigned because of
       unchanged v, and remain 0.
    3) An etrigger that's set to break on a VU-mode trap won't match
       properly because prev_v is incorrect

This be used in a forthcoming patch for trigger matching.

riscv/processor.cc

@@ -197,7 +197,7 @@ void state_t::reset(processor_t* const proc, reg_t max_isa)
   auto xlen = proc->get_isa().get_max_xlen();
 
   prv = PRV_M;
-  v = false;
+  v = prev_v = false;
   csrmap[CSR_MISA] = misa = std::make_shared<misa_csr_t>(proc, CSR_MISA, max_isa);
   mstatus = std::make_shared<mstatus_csr_t>(proc, CSR_MSTATUS);
 
@@ -747,17 +747,16 @@ void processor_t::set_virt(bool virt)
   if (state.prv == PRV_M)
     return;
 
-  if (state.v != virt) {
-    /*
-     * Ideally, we should flush TLB here but we don't need it because
-     * set_virt() is always used in conjucter with set_privilege() and
-     * set_privilege() will flush TLB unconditionally.
-     *
-     * The virtualized sstatus register also relies on this TLB flush,
-     * since changing V might change sstatus.MXR and sstatus.SUM.
-     */
-    state.v = virt;
-  }
+  /*
+    * Ideally, we should flush TLB here but we don't need it because
+    * set_virt() is always used in conjucter with set_privilege() and
+    * set_privilege() will flush TLB unconditionally.
+    *
+    * The virtualized sstatus register also relies on this TLB flush,
+    * since changing V might change sstatus.MXR and sstatus.SUM.
+    */
+  state.prev_v = state.v;
+  state.v = virt;
 }
 
 void processor_t::enter_debug_mode(uint8_t cause)

riscv/processor.h

@@ -84,6 +84,7 @@ struct state_t
   std::unordered_map<reg_t, csr_t_p> csrmap;
   reg_t prv;    // TODO: Can this be an enum instead?
   bool v;
+  bool prev_v;
   misa_csr_t_p misa;
   mstatus_csr_t_p mstatus;
   csr_t_p mstatush;